Projects

Description.

  • Accelerator  for DNA Sequence Alignment

    One of the most popular operations in personalized medicine is protein or DNA sequence database search based on pair-wise alignment, where a query sequence is compared with a database of sequences to find a highest-similarity sequence. This similarity can provide insights on the functionality of the query protein or the role of a gene. Conventional computer architecture is proven to be inefficient for personalized medicine tasks. For example, aligning even...
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  • A Compliance CC for ReRAM Characterization

    ReRAM is an emerging technology in both Industrial and academic communities. Compliance current (CC) is a factor that can significantly influence ReRAM potential performance. The goal of this project is to design and implement a CC measurement circuit and to perform CC measurements on ReRAM devices.
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  • STT-MRAM Based Multistate Register

    Resistive memories are non-volatile, dense, and CMOS compatible devices capable of addressing the scaling challenges of traditional CMOS memories. Spin torque transfer magnetoresistive RAM (STT-MRAM) is particularly advantageous for microprocessor memory structures due to the near infinite write endurance and CMOS compatible voltage levels. These devices, however, are constrained by relatively long and unpredictable write latencies that hinder integration of these devices within critical in-core applications. Just a few months...
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  • DNA Sequencing Accelerator For Long Read

    One of the most popular operations in personalized medicine is protein or DNA sequence database search based on pair-wise alignment, where a query sequence is compared with a database of sequences to find a highest-similarity sequence. OLC-based assembly algorithms focus on finding the read-to-read overlaps, defined to be a common sequence between two reads. A read-to-read overlap is a sequence match between two reads, and occurs when local regions on...
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  • Design of Microprocessor using Fast Path-Based Neural Branch Prediction

    Modern computer architectures increasingly rely on speculation to boost instruction-level parallelism. One of the common methods is the branch prediction. There are several ways to predict whether a branch is taken or not-taken, which significantly reduce the penalty of the branch. In this project we will develop a branch prediction that is bases on neural-network. The Fast Path-Based Neural Branch Prediction can reach 5% to 7% percent misprediction depending on...
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  • Design of Microprocessor with a Decoded Instruction Cache

    A CISC decoder is typically set up as a state machine. The machine reads the opcode field to determine what type of instruction it is, and where the other data values are. The instruction word is read in piece by piece, and decisions are made at each stage as to how the remainder of the instruction word will be read. One method to alleviate this is to use a decoded...
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  • Cyber Protection Chip

    The goal of this project is the development of an autonomous cyber protection chip for computer systems and communication channels linked to the cloud. Background: Current technology drives the accelerated development of computer components with increasing processing capabilities, bandwidth and high level of connectivity between components that maintain a constant link to the cloud. Such systems present a significant challenge in protecting the proper operation of the components. The purpose...
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  • Systolic Array For Deep Learning

    A systolyic array is an homogenous array of identical processors each performing the same function and each connected to several neighbours. Such a structure is very suitable for fast and efficient implementation of machine learning algorithms. The goal of this project is to design and implement an architecture for the computation of the convolution stage of a neural network for deep learning.
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  • Efficient Minimization of Conflicting Assumptions in MiniSAT

    Efficient Minimization of Conflicting Assumptions in MiniSAT

    Boolean Satisfiability (SAT) is the problem of deciding if there is an assignment to the variables of a Boolean formula such that the formula evaluated to TRUE. SAT is the classical NP-complete problem, and so it is unlikely that there is a polynomial-time algorithm that solves every SAT instance. Nevertheless, there are very efficient heuristic SAT-algorithms (SAT-solvers) that are able to solve practical instances with millions of variables and clauses....
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  • Implementation of A Genetic Algorithm for Channel Routing in VLSI Circuits

    In computer science, a genetic algorithm (GA) is a metaheuristic inspired by the process of natural selection. Genetic algorithms are commonly used to generate high-quality solutions to optimization. They rely on on bio-inspired operators such as mutation, crossover and selection. The purpose of this project is to implement a genetic algorithm to solve the channel routing problem.
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  • Deep Convolutional Neural Networks (DCNNs) For Embedded and Portable Systems

    Stochastic Computing (SC), which uses a bit-stream to represent a number within [-1, 1] by counting the number of ones in the bit-stream, has high potential for implementing CNNs with ultra-low hardware footprint. Since multiplications and additions can be calculated using AND gates and multiplexers in SC, significant reductions in power (energy) and hardware footprint can be achieved compared to the conventional binary arithmetic implementations. In this project we will...
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  • Efficient Minimization of Conflicting Assumptions in MiniSAT

    Boolean Satisfiability (SAT) is the problem of deciding if there is an assignment to the variables of a Boolean formula such that the formula evaluated to TRUE. SAT is the classical NP-complete problem, and so it is unlikely that there is a polynomial-time algorithm that solves every SAT instance. Nevertheless, there are very efficient heuristic SAT-algorithms (SAT-solvers) that are able to solve practical instances with millions of variables and clauses....
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  • Microprocessor Test Scenario Generation using Machine Learning Techniques

    A group in Intel is working on x86 test content optimization and creation using ML techniques. A working solution already exists for test content optimization  in production mode. The next stage of the project is to create new content automatically by learning from legacy content (since x86 is backward compatible, huge legacy is available to learn from). Test optimization refers to the compilation of a test suit that achieves the...
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  • Reconfigurable Voltage-Controlled Oscillator using Memristors

    The growing demand to connect the world is pushing wireless systems to be smaller than ever. This is part of the increasing move to a data driven world with billions of connected devices in the era of the Internet of Things (IoT) and space and energy are critical design criteria. Traditionally, miniaturization was possible owing to a focus in a single frequency and a single communication protocol. However, the real...
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  • Dual-Band Patch Antenna using Phase Change Material Based Switches

    Reconfigurable RF integrated circuits are an attractive feature for sustaining the increasing number of standards and functionalities of modern mobile devices. While back-end circuits in a radio transceiver (e.g., baseband analog, IF and digital) can be reconfigured using MOSFET switches, front-end circuits require high performance switches since resonant narrowband circuits require high quality factor inductors and capacitors. Phase-change-materials (PCM)-based RF switches have been proposed as high-performance RF switches due to...
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  • Design of Negative Impedance Converter

    The negative impedance converter (NIC) is a one-port Op-Amp circuit acting as a negative load which injects energy into circuits in contrast to an ordinary load that consumes energy from them. This is achieved by adding or subtracting excessive varying voltage in series to the voltage drop across an equivalent positive impedance. This reverses the voltage polarity or the current direction of the port and introduces a phase shift of...
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  • Low-Power Stochastic Computing for Convolutional Neural Networks Implementation

    With the recent advance of wearable devices and Internet of Things (IoTs), it becomes attractive to implement the Deep Convolutional Neural Networks (DCNNs) in embedded and portable systems. Currently, executing the software-based DCNNs requires high-performance and high-power servers. Stochastic Computing (SC), which uses a bit-stream to represent a number within [-1, 1] by counting the number of ones in the bit-stream, has high potential for implementing CNNs with ultra-low hardware...
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  • An Advanced Hardware Accelerator for Gradient Descent for Deep-learning

    An advanced scalable hardware accelerator for mini batch gradient descent, targets deep-learning applications. Deep neural networks are being widely used in a large number of applications for analyzing and extracting useful information from large amount of data that is being generated every day. Inference and training are the two modes of operation of a neural network. Training is the most computationally challenging task as it involves solving a large-scale optimization...
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  • Tunable Microwave Filters using Phase Change Material-based Switches

    Reconfigurable RF integrated circuits are an attractive feature to sustain the increasing number of standards and functionalities of modern mobile devices. While back-end circuits in a radio transceiver (e.g., baseband analog, IF and digital) can be reconfigured using MOSFET switches, front-end circuits require high performance switches since resonant narrowband circuits require high quality factor inductors and capacitors. Phase-change-materials (PCM)-based RF switches have been proposed as high-performance RF switches due to...
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  • הגדרה ומימוש של מעבד מקדים עבור מערכות חישה מרובות סנסורים

    מערכות חישה מתקדמות בנויות ממספר הולך וגדל של טכנולוגיות חישה שונות, כגון - EO/IR/SAR. לכל טכנולוגיה ישנן יתרונות וחסרונות: - למשל מצלמת יום מאפשרת לקבל תמונה ברזולוציה מרחבית טובה מאוד בדו-מימד אך רגישה מאוד לתנאי סביבה ואינה מסוגלת לבצע הפרדה תלת מימדית - מצלמת LWIR) long wave IR) מאפשרת זיהוי אובייקטים בטמפרטורות שונות ורגישותה לתנאי סביבה טובה יותר מאשר מצלמה אופטית רגילה. - מצלמת מכ"ם (SAR) מאפשרת לקבל תמונה בכל...
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  • Optimization of  String Key Comparison

    Optimization of  String Key Comparison

    Ordered data structures that index string keys are widespread, and provide the backbone for databases. Lookups on such data structures (e.g., balanced tree) is characterized by accessing keys that are very different from each other, at least until the traversal zooms on a small range of adjacent keys. When searching for a certain key, most comparisons are thus likely to determine the result (bigger or smaller) quickly. Many string implementations...
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  • Implementation of a Static Timing Analyser

    Static timing analysis is a crucial step in VLSI circuit design. It is used for validation of circuit timing requirements so that the manufactured circuit works correctly with pre-defined clock frequency. Static timing analysis is performed in different stages of VLSI design process, starting from logic description of the circuit and up to the full circuit with implemented placement and routing. In this project, students will implement a simplified timing...
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  • A Library for Layout Operations with TCL Interface

    Project description: Layout is the physical representation of VLSI circuit, in which all kinds of electronic devices – transistors, capacitances, resistances as well as interconnects are represented by rectangular polygons made of different materials used in semiconductor technology: different kinds of doped silicon, metals and insulators. For example, a layout of CMOS inverter is shown in the picture below. The layout shows “top view” of all polygons located at different...
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  • Placement Using an Artificial Neural Network

    Placement Using an Artificial Neural Network

    The first steps in the physical design of VLSI chips are partitioning and floorplanning. Partitioning is the process of dividing the chip into smaller pieces so that each piece is easier and faster to run. Floorplaning is the process of providing a shape to each piece so that the sum of the pieces is the entire chip and there are no overlaps. Artificial neural networks is a kind of a...
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  • Floorplan using Placement Algorithms

    Floorplan using Placement Algorithms

    The first steps in the physical design of VLSI chips are portioning and floorplanning. Partitioning is the process of dividing the chip into smaller pieces so that each piece is easier and faster to run. Floorplaning is the process of providing a shape to each piece so that the sum of the pieces is the entire chip and there are no overlaps The object of this project is to perform...
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  • Implementation of a Static Timing Analyser

    Static timing analysis is a crucial step in VLSI circuit design. It is used for validation of circuit timing requirements so that the manufactured circuit works correctly with pre-defined clock frequency. Static timing analysis is performed in different stages of VLSI design process, starting from logic description of the circuit and up to the full circuit with implemented placement and routing. In this project, students will implement a simplified timing...
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  • Stage Delay Calculator

    The performance of integrated circuits is one of the most important design objectives in modern VLSI design. Because of very high frequencies of today’s VLSI circuits, state-of-the-art timing analysis and simulation tools should perform delay and slope calculations with very high accuracy. For this, the timing analysis tools should have two main abilities: 1) stage (cell + interconnect it drives) delay modeling and 2) methods for delay / slope propagation...
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  • Power-Aware Clock Tree Synthesis 

    Clock is the crucial component of any modern VLSI circuit. Clock distribution network is usually has a form of a mutli-stage buffer tree with main clock driver at the root and clock consumers (sequential elements – flip-flops and latches) at leafs. The process of creation of the clock tree is called Clock Tree Synthesis (CTS) and it is very important stage in VLSI design process. The CTS problem can be...
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  • Thermal-Aware VLSI Floorplanning

    Thermal-Aware VLSI Floorplanning

    The first steps in the physical design of VLSI chips are partitioning and floorplanning. Partitioning is the process of dividing the chip into smaller pieces so that each piece is easier and faster to run. Floorplaning is the process of providing a shape to each piece so that the sum of the pieces is the entire chip and there are no overlaps The object of this project is to perform...
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  • A Real-Time Night Vision Camera Control System

    A novel night vision low resolution camera is being developed in Technion. It is based on a thermally isolated floating MOS transistor used to sense temperature changes as a result of external Infrared radiation. When a constant voltage is applied to the transistor, its current signal follows the temperature variations. This current signal is read out and amplified before further processing. This is done by an integrated readout circuit (ROIC).
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  • Automatic Verification of the Interrupt Cause Tree

    Automatic Verification of the Interrupt Cause Tree

    One of the most important tools of managing ASIC systems is interrupt verification. An interrupt event is normally a single event, sometimes more but still only several at the most. The causes for the interrupt are many (in our device it can get to a few thousands and more). To indicate the cause of the interrupt, there exists a hierarchy (tree) of registers where each bit in node register points...
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  • Contacts Electromagnetic Influences Modeling of CNT-FET

    Recent research in nanoelectronics has begun to explore the potential of carbon nanotube field effect transistors (CNFETs) as a successor to CMOS. Studies of individual carbon nanotubes have demonstrated that they have excellent electrical properties, including high electron mobility. Experiments with CNFETs have further demonstrated that these devices have large transconductances, which indicates a great potential for nanoelectronic circuits. One of the challenges the CNT-FET industry is facing these days...
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  • בניית מודל מאיץ אלקטרונים לצרכים רפואיים ב- HFSS

    המימדים הגדולים והמחיר הגבוה של מיכשור מודרני לטיפול בסרטן ע"י הקרנה (רדיותרפיה), נגזרים בעיקר ממאיץ האלקטרונים. טכניקות ההאצה שבשימוש היום מכתיבות מאיץ באורך של מטר כדי ליצר קרינה בעלת אנרגיה גבוהה מספיק לטיפול. מחקר שמתבצע בימים אלה בפקולטה, עוסק בפיתוח מאיץ המסוגל להאיץ אלקטרונים לאנרגיות גבוהות באמצאות לייזר ומוליך גלים דיאלקטרי.
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  • ממיר אותות אנלוגי לדיגטלי בקצבים גבוהים

    המעבדה מציעה פרויקטים בתחום המעגלים המשולבים בתדר רדיו הכוללים תכן של מעגלי תקשורת בתהליכי CMOS מתקדמים בתחום הננומטרי כמו 40nm ו- 28nm. הפרויקט כולל שלב של איפיון ובחינת טופולוגיות תכנוניות , ביצוע תכנון בכלי CAD מרכזיים כמו Virtuoso של Cadence ו- ADS של Keysight ,יישום תוך הכנסת שיקולי layout ובמקרים מסוימים (ורק עבור פרויקט שנתי) תהיה גם אפשרות ייצור השבב ובדיקתו. הבדיקות יתבצעו באמצעות ציוד מיוחד לבדיקת שבבים ותדר גבוה...
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  • מגבר דל רחש (LNA )  לתקשורת 5G ומכמים

    המעבדה מציעה פרויקטים בתחום המעגלים המשולבים בתדר רדיו הכוללים תכן של מעגלי תקשורת בתהליכי CMOS מתקדמים בתחום הננומטרי כמו 40nm ו- 28nm. הפרויקט כולל שלב של איפיון ובחינת טופולוגיות תכנוניות , ביצוע תכנון בכלי CAD מרכזיים כמו Virtuoso של Cadence ו- ADS של Keysight ,יישום תוך הכנסת שיקולי layout ובמקרים מסוימים (ורק עבור פרויקט שנתי) תהיה גם אפשרות ייצור השבב ובדיקתו. הבדיקות יתבצעו באמצעות ציוד מיוחד לבדיקת שבבים ותדר גבוה...
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  • מגבר הספק לתקשורת 5G ומכמים

    המעבדה מציעה פרויקטים בתחום המעגלים המשולבים בתדר רדיו הכוללים תכן של מעגלי תקשורת בתהליכי CMOS מתקדמים בתחום הננומטרי כמו 40nm ו- 28nm. הפרויקט כולל שלב של איפיון ובחינת טופולוגיות תכנוניות , ביצוע תכנון בכלי CAD מרכזיים כמו Virtuoso של Cadence ו- ADS של Keysight ,יישום תוך הכנסת שיקולי layout ובמקרים מסוימים (ורק עבור פרויקט שנתי) תהיה גם אפשרות ייצור השבב ובדיקתו. הבדיקות יתבצעו באמצעות ציוד מיוחד לבדיקת שבבים ותדר גבוה...
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  • Memristor-based Phase Shifters

    The growing demand to connect up the world is pushing wireless systems to be smaller than ever. This is part of the increasing move to a data driven world with billions of connected devices in the era of the Internet of Things (IoT) and space and energy are critical design criteria. Traditionally, miniaturization was possible owing to a focus in a single frequency and a single communication protocol. However, the...
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  • Memristor-based Tunable CMOS RF Amplifiers

    The growing demand to connect up the world is pushing wireless systems to be smaller than ever. This is part of the increasing move to a data driven world with billions of connected devices in the era of the Internet of Things (IoT) and space and energy are critical design criteria. Traditionally, miniaturization was possible owing to a focus in a single frequency and a single communication protocol. However, the...
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  • Design of an Arithmetic Logic Unit using Complementary Memristor Ratioed Logic

    Memristors are resistive devices with varying resistance which depends on the voltage applied to the device. The most natural memristor application is memory. However memristors can also be used for other applications, for example logic circuits. Once such approach is MRL (Memristor Ratioed Logic) - a hybrid CMOS-memristive logic family. In MRL, OR and AND logic gates are designed using memristors. The limitation of MRL is that every memristor-based logic...
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  • High Precision Differential Sense Amplifier for Resistive Memories

    Resistive memory is a new technology based on a passive circuit element called Memristor, which changes its resistance value based on the current flowing through it. Memristors are nanoscale elements that can be easily integrated in a typical VLSI manufacturing process. Therefore, memristors can be combined with existing structures to create new circuits. Memristors have a list of unique properties, such as non-volatility, non-linearity and sensitivity to process that make...
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  • Capacitive TMOS IR Sensing

    The Technion's innovative TMOS sensors utilize the widely available and affordable CMOS-SOI technology together with MEMS micromachining to a achieve break-through in passive IR imaging. The CMOS-SOI technology allows integration of the 2D sensors focal plane array matrix with the analog readout, which the subject of this project. Many types of sensors use capacitive sensing, including sensors used to detect and measure proximity, position or displacement, humidity, fluid level, and...
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  • Channel ReadOut Circuits for GMOS Sensor

    GMOS is a new gas sensor developed at the Technion. It is based on a thermally isolated floating MOS transistor used to sense temperature changes as a result of a chemical reaction that takes place when the gas comes in direct contact with the sensor. When a constant voltage is applied to the transistor, its current signal follows the temperature variations. This current signal should be read out and amplified...
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  • Sigma Delta Algorithmic ADC Conversion

    This project deals with the design and optimization of ∆∑ Algorithmic ADC conversion using the 0.18um STM technology. Delta-sigma modulation for analog-to-digital conversion resolves a number of bits which is logarithmic in the number of modulation cycles, and is linear with respect to the modulation order. As an alternative to higher-order noise shaping, an algorithmic scheme is proposed that iteratively resamples the modulation residue, by feeding the integrator output back...
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  • Fast Gain-Cell Design for eDRAM-centric Design

    Fast Gain-Cell Design for eDRAM-centric Design

    The need for SRAM replacement This proposal aims at replacing SRAM technology by Gain-Cell (GC) Embedded DRAM (eDRAM) in processors design. While the demand for on-die storage is increasing, the supply voltage has reached deep sub-volt level, where SRAM cells are susceptible to data corruption and information loss. Increasing the supply voltage is out of consideration since it causes dramatic increase in power consumption. We suggest replacing SRAM by GCeDRAM,...
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  • Differential High Speed Receiver Amplifier for SERDES in 10Gbps Applications

    As the demand for high throughput increases for applications like HD 4K, VR glass, signal processing in autonomous car, a high speed chip to chip interface become a bottleneck for data transfer between components. Few examples includes RF front end communication with the application processor SOC, FPGA accelerator communications with display chip/memory, high definition 3D camera communications with DSP chip and more. In order to support the high data throughput,...
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  • A Real-Time Night Vision Camera Control System

    A novel night vision low resolution camera is being developed in Technion. It is based on a thermally isolated floating MOS transistor used to sense temperature changes as a result of external Infrared radiation. When a constant voltage is applied to the transistor, its current signal follows the temperature variations. This current signal is read out and amplified before further processing. This is done by an integrated readout circuit (ROIC).
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  • Mixed Signal Readout System for IR Camera Based on Verilog/VHDL

    The Technion's innovative TMOS sensors utilize widely available and affordable CMOS-SOI technology together with MEMS micromachining to achieve break-through in passive IR imaging. The CMOS-SOI technology allows the integration of the 2D sensors focal plane array matrix with the analog readout, which is the subject of this project. In this project, you will design, implement and simulate top level architecture for an IR camera system that includes 10x10 matrix of...
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  • Improvement of Power/Performance in RSA Encryption Using CNFET Technology

    Although advances with silicon-based electronics continue to be made, alternative technologies are being explored. Digital circuits based on transistors fabricated from carbon nanotubes (CNTs) have the potential to outperform silicon by improving the energy–delay product, a metric of energy efficiency, by more than an order of magnitude. Hence, CNTs are an exciting complement to existing semiconductor technologies. In order to evaluate the potential of CNFETs to replace silicon CMOS technology,...
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  • Reverse Engineering Overcoming Scan Compression Structures

    A vast majority of the modern digital VLSI devices utilize a technique called 'full scan' for production testing. This technique concatenates all the device registers (flip-flops or latches) in a few shift registers called 'scan chains'. In this configuration, a production tester may use the scan chains to drive logic values to the inputs of combinatorial circuits, sample the results from their outputs, output the results via the same scan...
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  • Design For Testability (DFT) for Logic System by Scan

    A vast majority of the modern digital VLSI devices utilize a technique called 'full scan' for production testing. This technique concatenates all the device registers (flip-flops or latches) in a few shift registers called 'scan chains'. In this configuration, a production tester may use the scan chains to drive logic values to the inputs of combinatorial circuits, sample the results from their outputs, output the results via the same scan...
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  • Design of an RSA Public-Key Encryption Processor

    The RSA algorithm stood out among asymmetric encryption systems as a conceptually simple and practical encryption and authentication method which provides a near perfect level of security. Public-key cryptographic systems, such as the RSA often involve modular exponentiation (Z = Ye mod n). This widely used and computational complex operation is  performed using successive modular multiplications (C = AB mod n). The performance of such cryptosystems is primarily determined by...
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  • Design of an RSA Public-Key Encryption Processor

    The RSA algorithm stood out among asymmetric encryption systems as a conceptually simple and practical encryption and authentication method which provides a near perfect level of security. Public-key cryptographic systems, such as the RSA often involve modular exponentiation (Z = Ye mod n). This widely used and computational complex operation is  performed using successive modular multiplications (C = AB mod n). The performance of such cryptosystems is primarily determined by...
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  • Multi-Channel IO Scheduler For Flash Memory

    Modern flash-based memories contain aggressive 19nm scaling of floating-gate transistors. When performing read/write/erase commands in a flash memory,  the chip is occupied and cannot be used to perform other commands in parallel. It is sometimes possible to stop the instruction execution in the middle (to perform another instruction) but the penalty of return is a significant slowdown of command execution. The SSD architecture consists of multiple channels. Each has multiple...
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  • Implementation of an Advanced Error Correction Algorithm For Flash Memory

    Modern flash-based memories contain aggressive 19nm scaling of floating-gate transistors. As a result, data is often stored with errors due to inter-cell interference, coupling, random-telegraph noise and more. The signal-to-noise ratio becomes even worse as density increases. In order to provide reliable data storage, system controller employs error-correcting algorithms. In this project, the students will implement a design of advanced error-correction encoder and decoder. The goal is to study and...
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  • NVMe Command Encoder/Decoder

    The NVM Express (NVMe) specification was introduced in 2011 and today it is the new standard storage interface for Solid-State Drives (SSD). The NVM Express specification defines a controller interface for PCIe SSD used for Enterprise and Client applications. It is based on a queue mechanism with advanced register interface, command set and feature set including error logging, status, system monitoring (SMART, health), and firmware management). The southbridge is one...
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  • Write-Once Memory (WOM)

    Write-Once Memory (WOM) code enable to transform information such that consecutive writes to the memory would have uni-directional transition of bits. This property is useful for SSD memory since it reduces the number of program-erase cycles, thus it increases the memory endurance and might and also performance impact. In this project, the students will do analysis/trade-off of new WOM codes efficiency and power/area/throughput comparison. The goal is to implement a...
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  • Architectural Exploration for Head of Line Blocking (HOLB) Solutions

    Problem Definition: Network routers by nature handle thousands of mega packets per second. Each packet might come from one port and be destined to another port. The actual routing decision is made only once the packet is received and inspected. This scheme by definition, causes head of line blocking, in which one packet destined to a blocked destination completely blocks the input queue or the common processing pipeline. These kinds...
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  • BCH Error Detection and Correction for SRAM

    The Bose, Chaudhuri, and Hocquenghem (BCH) codes form a large class of powerful random error-correcting cyclic codes. This class of codes is a remarkable generalization of the Hamming code for multiple-error correction. BCH codes are used in varied applications such as satellite communications, compact disc players, DVDs, disk drives, solid-state drives, two-dimensional bar codes, SRAMs, etc. This project proposes building a designated BCH IP core, which can be configured to...
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  • Implementation of a Digital OFDM Transciever

    Orthogonal Frequency Division Multiplexing (OFDM) is a Frequency Division Multiplexing (FDM) technique used as a digital multi-carrier modulation method. Instead of using one high speed channel, the data is split into a large number of lower speed channels. Orthogonal sub carriers are used to carry data on several parallel data streams which allows more efficient use of the spectrum compare to regular FDM. Orthogonality of the carriers prevents interference between...
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  • הגדרה ומימוש של מעבד מקדים עבור מערכות חישה מרובות סנסורים

    מערכות חישה מתקדמות בנויות ממספר הולך וגדל של טכנולוגיות חישה שונות, כגון - EO/IR/SAR. לכל טכנולוגיה ישנן יתרונות וחסרונות: - למשל מצלמת יום מאפשרת לקבל תמונה ברזולוציה מרחבית טובה מאוד בדו-מימד אך רגישה מאוד לתנאי סביבה ואינה מסוגלת לבצע הפרדה תלת מימדית - מצלמת LWIR) long wave IR) מאפשרת זיהוי אובייקטים בטמפרטורות שונות ורגישותה לתנאי סביבה טובה יותר מאשר מצלמה אופטית רגילה. - מצלמת מכ"ם (SAR) מאפשרת לקבל תמונה בכל...
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  • Implementation of a Smallest Univalue Segment Assimilating Nucleus (SUSAN) Block

    Implementation of a Smallest Univalue Segment Assimilating Nucleus (SUSAN) Block

    Edge and feature extraction is one of the most important first steps in computer vision. Its main objective is to find as many useful features from a scene while keeping the output noise level to a minimum. Edge, corner and vertex detection processes serve to simplify the analysis of images by drastically reducing the amount of data to be processed.  The SUSAN principle is the basis for algorithms to perform...
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  • Design of an Arithmetic Logic Unit using Complementary Memristor Ratioed Logic

    Memristors are resistive devices with varying resistance which depends on the voltage applied to the device. The most natural memristor application is memory. However memristors can also be used for other applications, for example logic circuits. Once such approach is MRL (Memristor Ratioed Logic) - a hybrid CMOS-memristive logic family. In MRL, OR and AND logic gates are designed using memristors. The limitation of MRL is that every memristor-based logic...
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  • Accelerator for GNSS Acquisition and Tracking

    An advanced Global-Navigation-Satellite-System (GNSS) accelerator, which provides the end user with improved position, velocity and time solutions. High performance conventional GPS/GNSS receivers rely on ASIC technology to implement massive correlators, as the performance of SDR solutions is still limited. With a reasonable distribution of tasks between the host hardware and reconfigurable peripherals, a higher performance is achieved. The figure illustrates a schematic structure of a GNSS receiver, where the proposed...
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  • מימוש מעבד נתונים ייעודי לצורך ביצוע רגולציה בזמן אמת על מסחר מבוסס מכונה בשוק ההון

    מערכות הסוחרות באופן אוטומטי בניירות ערך שינו מן היסוד את פעילות שוק ההון בשנים האחרונות. רוב המסחר בבורסות האמריקאיות מתנהל כיום ללא כל מעורבות אנושית. מכונות המסחר יכולות להיות מתוכננות לסחור במניות, אופציות, חוזים עתידיים ומוצרי מט"ח המבוססים על אוסף של כללים מוגדר מראש  הקובעים מתי לקנות, מתי למכור וכמה כסף להשקיע בכל מוצר מסחר. מערכות המסחר האוטומטיות הולכות ומשתכללות תוך עיבוד נתונים בכמות ובקצב הולכים וגדלים יחד עם קיצור...
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  • Design of Quad-Core Microprocessor

    As the manufacturing technologies of VLSI progresses, HW architects are constantly looking for ways to improve overall performance of the CPU. In the past, many small scale architecture improvements, as well as pipelines, and other methods were used to improve performance. Other methods were increasing clock frequency and the width of data-bus, from 16 bit to 32, 64 and higher. As the manufacturing processes become more and more dense,  and...
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  • Design of an RSA Public-Key Encryption Processor

    The RSA algorithm stood out among asymmetric encryption systems as a conceptually simple and practical encryption and authentication method which provides a near perfect level of security. Public-key cryptographic systems, such as the RSA often involve modular exponentiation (Z = Ye mod n). This widely used and computational complex operation is  performed using successive modular multiplications (C = AB mod n). The performance of such cryptosystems is primarily determined by...
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  • Optical G-MOS Gas Sensor in CMOS-SOI-MEMS Technology

    In this project, you will implement optical G-MOS detectors based on CMOS-SOI-MEMS technology. You will be responsible for the device coupled electrical/thermal and mechanical behavior requirements, analysis and specifications definition.
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  • 3D Flash Memory Management

    The goal of this project is to design an algorithm to detect and correct such errors. The scheme relies on a coding technique that incorporates the side information of fast detrapping during the encoding stage. The implementation includes matlab modeling, spec and architecture definition, logic design using the Verilog HDL, verification and synthesis.
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  • Emerging Memory Technology Controller

    The goal of this project is to develop algorithms for performance enhancement/cost reduction and implement it on HDL for related memory controller. The implementation includes matlab modeling, spec and architecture definition, logic design using the Verilog HDL, verification and synthesis. The emphasis of this project will be on low latency of the design.
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  • Hack Proof RSA Public Key Encryption System

    Description: In the field of cryptanalysis the tools utilized to recover the secret information are very different from the ones utilized to build the cipher. For the most part cryptanalysis is based on probabilistic Bayesian techniques. In this method some information leaked from the system is exploited in order to derive a slight probability advantage of one code over another. Accordingly, after a sufficient number of ciphertext messages are analyzed,...
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  • Power Amplifier for 5G Communications and Radar

      Background information: Project description: המעבדה מציעה פרויקטים בתחום המעגלים המשולבים בתדר רדיו הכוללים תכן של מעגלי תקשורת בתהליכי CMOS מתקדמים בתחום הננומטרי כמו 40nm ו- 28nm. הפרויקט כולל שלב של איפיון ובחינת טופולוגיות תכנוניות , ביצוע תכנון בכלי CAD מרכזיים כמו Virtuoso של Cadence ו- ADS של Keysight ,יישום תוך הכנסת שיקולי layout ובמקרים מסוימים (ורק עבור פרויקט שנתי) תהיה גם אפשרות ייצור השבב ובדיקתו. הבדיקות יתבצעו באמצעות ציוד...
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  • A Library for Layout Operations with TCL Interface

    Project description: Layout is the physical representation of VLSI circuit, in which all kinds of electronic devices – transistors, capacitances, resistances as well as interconnects are represented by rectangular polygons made of different materials used in semiconductor technology: different kinds of doped silicon, metals and insulators. For example, a layout of CMOS inverter is shown in the picture below. The layout shows “top view” of all polygons located at different...
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  • Design Rules Checker Tool

    Project description: Layout is the physical representation of VLSI circuit, in which all kinds of electronic devices – transistors, capacitances, resistances as well as interconnects are represented by rectangular polygons made of different materials used in semiconductor technology: different kinds of doped silicon, metals and insulators. For example, a layout of CMOS inverter is shown in the picture below. The layout shows “top view” of all polygons located at different...
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  • Backend Implementation of an OpenSPARC T1-Based SoC

    Description: The project is an OpenSPARC T1-based SoC which includes: – Full or reduced OpenSPARC T1 CPU core – OpenSPARC FPU – Bridge to connect the CPU and FPU to the Whisbone bus – Nor flash controller – UART – OpenCores ethernet controller – Bridges from Whishbone to Altera and Xilinx DRAM controllers The goal of this project is to perform the complete backend design of a OpenSPARC T1 microprocessor...
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