This project deals with the design and optimization of ∆∑ Algorithmic ADC conversion using the 0.18um STM technology.
Delta-sigma modulation for analog-to-digital conversion resolves a number of bits which is logarithmic in the number of modulation cycles, and is linear with respect to the modulation order. As an alternative to higher-order noise shaping, an algorithmic scheme is proposed that iteratively resamples the modulation residue, by feeding the integrator output back to the input. This yields one bit of resolution linear in the number of cycles, similar to an algorithmic analog-to-digital converter.
The schematic simplifies the design of the digital decimator to a single shifting counter, and avoids interstage gain errors in conventional algorithmic analog-to-digital converters. It is possible to implement a CMOS array of 128 converters suitable for large-scale parallel quantization in digital imaging and hybrid analog-digital computing.
The project requirements include the implementation and analysis of the proposed architecture which will be analyzed during evaluation study. Next the design will be implemented in layout. The circuits should be designed under required performance constraints of minimal power, layout area, signal crosstalk and noise reduction. Circuit design and simulations and analog layout will be done using Cadence tools.
Recommended courses: Introduction to VLSI