
The goal of this experiment is to introduce the students to the so called "Backend Design" of a VLSI chip. The backend design involves two main stages, namely synthesis and physical design (automatic place and route) which in turn are composed of numerous sub-stages. The students will be give the RTL implementation of an accelerator for a machine learning system and will perform all the following steps:
Synthesis:
- DFT : design for testability
- Timing Analysis
- Logical equivalence checking
Physical Design (Automatic Layout):
- Floorplanning
- Power grid design
- Macro block and standard cell placement
- Clock tree synthesis
- Timing optimizations (setup, hold and ECO corrections)
- Power analysis
This final result will be a complete layout ready for fabrication.