Computer Architecture Archives

Design and Implementation of a Superscalar Hack Processor

In this project is to enhance the architecture of the simple "Hack Microprocessor". The goal is not to simply duplicate the data path but to put a lot of thought on the control path and architectural planning to allow the implementation of an optimal architecture. Some challenges include efficient resolution of hazards and branch handling.

The Design of a Ring Controller to Support a Multi-core RISC-V Implementation in a Ring Configuration

The goal of this project is to design and implement an RTL IP (System Verilog) that will enable multiple instances of RISC-V cores to be connected in a ring configuration. The IP will consist of two main interfaces – on the one side the “Core” and the other the “Ring”. The Ring Interface will manage the data transactions on the ring - pushing and pulling RD/WR/RD_RSP transactions to/from the ring....

Categories: 236381 | Computer Architecture | Digital | Microprocessors

Sort Algorithm for Memristive Memory Processing Unit

The Memristive Memory Processing Unit (mMPU) is a new process-in-memory computer architecture, which performs the computation without moving the data from the computer’s main memory (RAM). The goal of the project is to develop a sort algorithm to run on an mMPU which is based on emerging memory technology of ReRAM.

Electromigration-Aware Architecture for Modern Microprocessors

In this project, we propose a new architecture that significantly improves reliability by reducing EM impact while relaxing the physical design efforts and significantly extending microprocessor lifetime. It is based on the observation that in many cases EM reliability issues result from excessive write activities or signals toggling in a non uniform manner. We will examine EM improvement to 3 main components of microprocessors: ALU execution unit, register file and...

Categories: Computer Architecture | Digital | Microprocessors

Dual Issue RISC-V Processor

RISC-V (pronounced "risk-five") is an open-source hardware instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles.The project began in 2010 at the University of California, Berkeley, but many contributors are volunteers not affiliated with the university. The goal of this project is to evaluate the enhanced performance of the double issue capability.

Categories: 236381 | Computer Architecture | Digital | Microprocessors

Power/ARM to RISC-V Assembly Converter

RISC-V is a classic RISC architecture rebuilt for modern times. At its heart is an array of 32 registers containing the processor's running state, the data being immediately operated on, and housekeeping information. RISC-V comes in 32-bit and 64-bit variants, with register size changing to match. A large amount of code has been developed and written at IBM in assembly for the PowerPC processor for which no C source-code exists....

Categories: 236381 | 236503 | Computer Architecture | Microprocessors | Software

Executing State Machines Within a Memristor-Based Memory

In this project, the students will design and implement an algorithm for executing state machines within a memristor-based memory. Such a novel method enables implementing a processor within the memory, thus eliminating the need for an external processor in small systems, and therefore reduces the limitations of today's computer systems.

Categories: 236503 | Computer Architecture | Digital | Memristors

Implementation of a Novel DNN Accelerator with Simultaneous Multi-threading

A deep neural network (DNN) is an artificial neural network (ANN) with multiple layers between the input and output layers. The DNN finds the correct mathematical manipulation to turn the input into the output, whether it be a linear relationship or a non-linear relationship. The goal of this project is to build a novel DNN accelerator with simultaneous multi-threading.

Categories: 236381 | Computer Architecture | Digital | Machine Learning

Architectural Simulator for Object Oriented Processor

The purpose of this project is to simulate the effect of changing several architecture components on the overall performance of the OOPc processor. Such parameters include: The amount of cores, the amount of simultaneous threads which can run on a core, the sizes of the internal memories and caches and the network on a chip topology.