Projects Archive

  • Year - 2021
  • The Bitlet model is a new an analytical, parameterized,  modeling tool, developed in the ASIC2 lab. The Bitlet model can be used to estimate the performance and the power of a PIM-based system and thereby assess the affinity of workloads for PIM as opposed to traditional computing.In order to make Bitlet more beneficial, it has to be made more accessible to users by equipping it with new features and interactive graphical...
  • In this project some alternative SC Integrator architectures will be analyzed during an evaluation study and the results will be compared. The circuits will be designed under required performance constraints of minimal power, layout area, signal cross talks and noise reduction using advanced IC technologies.
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  • In this project some alternative low voltage thermal sensor circuits architectures will be analyzed during an evaluation study and the results will be compared. The circuits will be designed under required performance constraints of minimal power, layout area, signal cross talks and noise reduction using advanced IC technologies.
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  • In this project, the RF model of the indirectly heated four-terminal PCM RF switch will be improved and verified against experimental data. The model will be unified with an electro-thermal model of the device to perform optimizations of the device structure for different applications. This model will be used to explore the design constraints of these devices and to find the optimum device geometries for different applications.
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  • Recently many novel memory technologies are emerging. For example ReRAM, STT-MRAM, DRAM. All these technologies are very suitable for  in memory processing. Unfortunately, at the present time, there  are no actual devices and so simulating in-memory processing with these technologies is very difficult. The goal of this project is to provide a model which can be used to perform these simulations.
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  • Reconfigurable RF integrated circuits are an attractive feature to sustain the increasing number of standards and functionalities of modern mobile devices. While back-end circuits in a radio transceiver (e.g., baseband analog, IF and digital) can be reconfigured using MOSFET switches, front-end circuits require high performance switches since resonant narrowband circuits require high quality factor inductors and capacitors. Phase-change-materials (PCM)-based RF switches have been proposed as high-performance RF switches due to...
  • In this project, you are required to design a systolic array that efficiently implements the logic required to support per-channel activation tensor quantization for a convolution neural network. You are required to implement the design using SystemVerilog, simulate and synthesize it after which the layout will be designed. Area, power, and energy will be analyzed and compared to a conventional systolic array. Skills you will acquire: SystemVerilog, Synopsys Design Compiler,...
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  • In this project, we propose a new architecture that significantly improves reliability by reducing EM impact while relaxing the physical design efforts and significantly extending microprocessor lifetime. It is based on the observation that in many cases EM reliability issues result from excessive write activities or signals toggling in a non uniform manner.  We will examine EM improvement to 3 main components of microprocessors: ALU execution unit, register file and...
  • In this project, theories of the cellular nonlinear network will be studied and the possibilities of using memristive devices in these networks will be investigated. A software model of prototype cellular nonlinear neural network accounting for the behaviors of memristive devices as the synaptic connections will be implemented and a series of simulations will be performed.
  • An advanced scalable hardware accelerator for deep Convolutional Auto-Encoder (CAE), targets deep-learning applications. Integrating a CAE hardware accelerator has advantages in resources occupation, operation speed, and power consumption, indicating great potential for application in digital signal processing. This project suggests building a designated acceleration IP, which efficiently performs RAM-to-RAM calculations in a pipeline fashion and thereby dramatically offloads machine-learning software applications.
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  • There are endless number of platforms that require implementation of video transformations, such as curved TV/computer/smartphone screens, goggles, pilot hamlet, etc. All these platforms require transformation of flat image to curved image that fits the display, so the user can see the image well without data loss. The main challenges of the core implementation are low latency (“video in => video out), high video resolutions and frame rate. The goal...
  • Hardware Trojan horses are a real concern for the last 12 years or so, especially for national security. . A few examples of what such a Trojan can do when triggered are : 1. Turn off security protections or insert a known key to the encryption engine; 2. Insert errors to cause malfunction of a critical infrastructure; 3: Leak information to an unprotected zone (for example from a privileged CPU...
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  • In computer science, a genetic algorithm (GA) is a metaheuristic inspired by the process of natural selection. Genetic algorithms are commonly used to generate high-quality solutions to optimization. They rely on on bio-inspired operators such as mutation, crossover and selection. The purpose of this project is to implement a genetic algorithm to solve the channel routing problem.
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  • An accurate, small, low-power CMOS temperature sensor for on-chip thermal monitoring will be designed and analyzed in this project. The temperature sensor utilizes the temperature characteristics of the threshold voltage of a MOS transistor to sense temperature and is quite linear over the in-temperature range (-20C, 100°C). In this project some alternative temperature sensor architectures will be analyzed during an evaluation study and the results will be compared.
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  • The performance of integrated circuits is one of the most important design objectives in modern VLSI design. Because of very high frequencies of today’s VLSI circuits, state-of-the-art timing analysis and simulation tools should perform delay and slope calculations with very high accuracy. For this, the timing analysis tools should have two main abilities: 1) stage (cell + interconnect it drives) delay modeling and 2) methods for delay / slope propagation...
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  • Recent research in nanoelectronics has begun exploring the potential of carbon nanotube field effect transistors (CNFETs) as a successor to CMOS. In order to evaluate the potential of CNFETs as an alternative to silicon CMOS technology, SPICE models of CNFETs have been developed. The goal of this project is to develop a smart algorithm, based on logic effort, to design circuits more efficiently for delay optimization.
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  • STT-MRAM writes to a memory array by manipulating electron spin with a polarizing current, performs like DRAM but requires no refresh, significant reduction in switching energy compared to FS Toggle MRAM, highly scalable, enabling higher density memory products (sampling 1Gb in 2019), can interface with JEDEC DDR3 with minor modification, and is  quite an attractive emerging memory. The goal of this project is to implement and simulate circuits using this device.
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  • Year - 2020
  • Project description:Template Matching is a method for searching and finding the location of a template image in a larger image. It relies on calculating at each position of the image under examination a correlation or distortion function that measures the degree of similarity or dissimilarity to a template sub-image.Among the correlation/distortion functions proposed in literature, Normalized Cross-Correlation (NCC) and Zero mean Normalized Cross Correlation (ZNCC) are widely used due to...
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  • The goal is to design and implement the HDL of a high-performance hardware serial divider for high frequencies. Initially, at least two different division algorithms will be investigated and analyzed. The design will be parametrized so that it can be configured according to specified requirements. The divider will support a variety of input / output number representation formats.
  • RISC-V (pronounced "risk-five") is an open-source hardware instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles.The project began in 2010 at the University of California, Berkeley, but many contributors are volunteers not affiliated with the university. The goal of this project is to evaluate the enhanced performance of the double issue capability.
  • In this project a tunable power amplification stage will be designed and evaluated. Both stabilization techniques and matching networks will be implemented by memristor-based circuits. The project is based on advanced research. The implementation will be done in Virtuoso and/or ADS.
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  • Recently many novel memory technologies are emerging. For example ReRAM, STT-MRAM, DRAM. All these technologies are very suitable for  in memory processing. Unfortunately, at the present time, there  are no actual devices and so simulating in-memory processing with these technologies is very difficult. The goal of this project is to provide a model which can be used to perform these simulations.
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  • Logic designs is usually comprised of two types of logic: data paths and control logic. During reverse engineering, we first try to locate the data path structures taking advantage of their regular structure. Finding these structures helps in locating major circuit elements, such as register files, adders, ALU, multipliers, etc. The distinguishing property of data paths is aggregation of bit-level operations into multibit word operations. In this project, we will...
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  • Problem Description: Network routers by nature handle thousands of mega packets per second. Each packet might come from one port and be destined to another port. The actual routing decision is made only once the packet is received and inspected. This scheme by definition, causes head of line blocking, in which one packet destined to a blocked destination completely blocks the input queue or the common processing pipeline. These kinds...
  • Reconfigurable RF integrated circuits are an attractive feature for sustaining the increasing number of standards and functionalities of modern mobile devices. While back-end circuits in a radio transceiver (e.g., baseband analog, IF and digital) can be reconfigured using MOSFET switches, front-end circuits require high performance switches since resonant narrowband circuits require high quality factor inductors and capacitors. Phase-change-materials (PCM)-based RF switches have been proposed as high-performance RF switches due to...
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  • The growing demand to connect the world is pushing wireless systems to be smaller than ever. This is part of the increasing move to a data driven world with billions of connected devices in the era of the Internet of Things (IoT) and space and energy are critical design criteria. Traditionally, miniaturization was possible owing to a focus in a single frequency and a single communication protocol. However, the real...
  • The NVM Express (NVMe) specification was introduced in 2011 and today it is the new standard storage interface for Solid-State Drives (SSD). The NVM Express specification defines a controller interface for PCIe SSD used for Enterprise and Client applications. It is based on a queue mechanism with advanced register interface, command set and feature set including error logging, status, system monitoring (SMART, health), and firmware management). The southbridge is one...
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  • Modern flash-based memories contain aggressive 19nm scaling of floating-gate transistors. When performing read/write/erase commands in a flash memory,  the chip is occupied and cannot be used to perform other commands in parallel. It is sometimes possible to stop the instruction execution in the middle (to perform another instruction) but the penalty of return is a significant slowdown of command execution. The SSD architecture consists of multiple channels. Each has multiple...
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  • A group in Intel is working on x86 test content optimization and creation using ML techniques. A working solution already exists for test content optimization  in production mode. The next stage of the project is to create new content automatically by learning from legacy content (since x86 is backward compatible, huge legacy is available to learn from). Test optimization refers to the compilation of a test suit that achieves the...
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  • The goal of this project is to perform the complete backend design of the OFDM transmitter chip and its integrated memories. This includes : synthesis, gate level simulation, physical (layout) design and verification, timing verification, power and power grid analysis. The chip may then be submitted for fabrication.  The implementation will be done in Tower CMOS 0.18u technology.
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  • A vast majority of the modern digital VLSI devices utilize a technique called 'full scan' for production testing. This technique concatenates all the device registers (flip-flops or latches) in a few shift registers called 'scan chains'. In this configuration, a production tester may use the scan chains to drive logic values to the inputs of combinatorial circuits, sample the results from their outputs, output the results via the same scan...
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  • As the demand for high throughput increases for applications like HD 4K, VR glass, signal processing in autonomous car, a high speed chip to chip interface become a bottleneck for data transfer between components. Few examples includes RF front end communication with the application processor SOC, FPGA accelerator communications with display chip/memory, high definition 3D camera communications with DSP chip and more. In order to support the high data throughput,...
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  • Resistive memory is a new technology based on a passive circuit element called Memristor, which changes its resistance value based on the current flowing through it. Memristors are nanoscale elements that can be easily integrated in a typical VLSI manufacturing process. Therefore, memristors can be combined with existing structures to create new circuits. Memristors have a list of unique properties, such as non-volatility, non-linearity and sensitivity to process that make...
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  • A systolyic array is an homogenous array of identical processors each performing the same function and each connected to several neighbours. Such a structure is very suitable for fast and efficient implementation of machine learning algorithms. The goal of this project is to design and implement an architecture for the computation of the convolution stage of a neural network for deep learning.
  • Stochastic Computing (SC), which uses a bit-stream to represent a number within [-1, 1] by counting the number of ones in the bit-stream, has high potential for implementing CNNs with ultra-low hardware footprint. Since multiplications and additions can be calculated using AND gates and multiplexers in SC, significant reductions in power (energy) and hardware footprint can be achieved compared to the conventional binary arithmetic implementations. In this project we will...
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  • The growing demand to connect up the world is pushing wireless systems to be smaller than ever. This is part of the increasing move to a data driven world with billions of connected devices in the era of the Internet of Things (IoT) and space and energy are critical design criteria. Traditionally, miniaturization was possible owing to a focus in a single frequency and a single communication protocol. However, the...
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  • המעבדה מציעה פרויקטים בתחום המעגלים המשולבים בתדר רדיו הכוללים תכן של מעגלי תקשורת בתהליכי CMOS מתקדמים בתחום הננומטרי כמו 40nm ו- 28nm. הפרויקט כולל שלב של איפיון ובחינת טופולוגיות תכנוניות , ביצוע תכנון בכלי CAD מרכזיים כמו Virtuoso של Cadence ו- ADS של Keysight ,יישום תוך הכנסת שיקולי layout ובמקרים מסוימים (ורק עבור פרויקט שנתי) תהיה גם אפשרות ייצור השבב ובדיקתו. הבדיקות יתבצעו באמצעות ציוד מיוחד לבדיקת שבבים ותדר גבוה...
  • One of the most popular operations in personalized medicine is protein or DNA sequence database search based on pair-wise alignment, where a query sequence is compared with a database of sequences to find a highest-similarity sequence. OLC-based assembly algorithms focus on finding the read-to-read overlaps, defined to be a common sequence between two reads. A read-to-read overlap is a sequence match between two reads, and occurs when local regions on...
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  • Modern computer architectures increasingly rely on speculation to boost instruction-level parallelism. One of the common methods is the branch prediction. There are several ways to predict whether a branch is taken or not-taken, which significantly reduce the penalty of the branch. In this project we will develop a branch prediction that is bases on neural-network. The Fast Path-Based Neural Branch Prediction can reach 5% to 7% percent misprediction depending on...
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  • A deep neural network (DNN) is an artificial neural network (ANN) with multiple layers between the input and output layers. The DNN finds the correct mathematical manipulation to turn the input into the output, whether it be a linear relationship or a non-linear relationship. The goal of this project is to build a novel DNN accelerator with simultaneous multi-threading.
  • A deep neural network (DNN) is an artificial neural network (ANN) with multiple layers between the input and output layers. The DNN finds the correct mathematical manipulation to turn the input into the output, whether it be a linear relationship or a non-linear relationship.Multiply-and-accumulate (MAC) operations are the core of deep neural networks (DNNs). In this project we would like to investigate to what extent the toggling of the MAC...
  • Performance aspects are becoming more and more relevant in modern hardware architectures and introduce various engineering challenges in the ASIC domain.Performance plays a central role in both pre-silicon and post-silicon phases and corresponds with embedded-software architecture (e.g. real-time QoS decisions). The performance widget displays data for performance metrics of mobile devices and can be configured to monitor any performance metric. This project proposes designing and implementing a designated Performance Widget...
  • The voltage-controlled oscillator (VCO) is a critical sub-block in communications transceivers. The role of the VCO in a transceiver and the VCO requirements will be reviewed and the necessity of GHz VCOs and the driving factors towards the monolithic integration of the VCO be examined. In addition, the VCO design techniques will be outlined and design trade-offs be explored.
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  • Boolean Satisfiability (SAT) is the problem of deciding if there is an assignment to the variables of a Boolean formula such that the formula evaluated to TRUE. SAT is the classical NP-complete problem, and so it is unlikely that there is a polynomial-time algorithm that solves every SAT instance. Nevertheless, there are very efficient heuristic SAT-algorithms (SAT-solvers) that are able to solve practical instances with millions of variables and clauses....
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  • In this project, the students will perform characterization of a Resistive RAM (ReRAM) Crossbar array. They will work with a packaged device that contains a few arrays. The measurement setup will be based on a set of SMUs (Source Measure Units)  and a PC platform that control the measuring equipment. The students will use Python to create a set of tool that allow for automatic parameter extraction from memristive devices...
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  • Reverse engineering of Integrated Circuits (IC's) is a complex process that involves multiple disciplines and skills. The input to the process is usually a physical device, and the output is a human-readable specification. At the first phase, the IC passes tear down to obtain a gate-level netlist description. In the second phase, a specification is extracted. The second stage is non-trivial and involves various learning algorithms and heuristics. The purpose...
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  • The global community produces digital data at increasing rates, creating enormous data centers for storage.Recent research proposes replacing the traditional data storage devices with biological DNA-based device, which can store information of the scale of a data-center within a few grams of weight.In this project, the student will study the emerging technological approach, and will implement digital controller circuits for managing DNA storage device. The main goals are understanding of...
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  • RISC-V (pronounced "risk-five") is an open-source hardware instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles.The project began in 2010 at the University of California, Berkeley, but many contributors are volunteers not affiliated with the university. The goal of this project is to study the RISC-V instruction set and then to design and implement a basic RISC-V microprocessor that supports all the instructions. Additional features will...
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  • ReRAM is an emerging technology in both Industrial and academic communities. Compliance current (CC) is a factor that can significantly influence ReRAM potential performance. The goal of this project is to design and implement a CC measurement circuit and to perform CC measurements on ReRAM devices.
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  • The goal of this project is to implement, study and experiment with different backtracking heuristics in the winner of the latest SAT evaluation contest (SAT Race 2019). We will try to find a backtracking heuristic, which would improve the performance of the already very efficient solver. It should be noticed that we won’t need to implement any new backtracking algorithm (as the complexity of such an implementation would go beyond...
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  • RISC-V is a classic RISC architecture rebuilt for modern times. At its heart is an array of 32 registers containing the processor's running state, the data being immediately operated on, and housekeeping information.  RISC-V comes in 32-bit and 64-bit variants, with register size changing to match. A large amount of code has  been developed and written at IBM in assembly for the PowerPC processor for which no C source-code exists....
  • RISC-V (pronounced "risk-five") is an open-source hardware instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles.The project began in 2010 at the University of California, Berkeley, but many contributors are volunteers not affiliated with the university. RISC-V, pronounced 'Risk-Five', is a new architecture that is available under open, free and non-restrictive licences. It has widespread industry support from chip and device makers, and is designed to...
  • The goal of this project is to develop algorithms for performance enhancement/cost reduction and implement it on HDL for related memory controller. The implementation includes matlab modeling, spec and architecture definition, logic design using the Verilog HDL, verification and synthesis. The emphasis of this project will be on low latency of the design.
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  • Year - 2019
  • As the manufacturing technologies of VLSI progresses, HW architects are constantly looking for ways to improve overall performance of the CPU. In the past, many small scale architecture improvements, as well as pipelines, and other methods were used to improve performance. Other methods were increasing clock frequency and the width of data-bus, from 16 bit to 32, 64 and higher. As the manufacturing processes become more and more dense,  and...
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  • With the recent advance of wearable devices and Internet of Things (IoTs), it becomes attractive to implement the Deep Convolutional Neural Networks (DCNNs) in embedded and portable systems. Currently, executing the software-based DCNNs requires high-performance and high-power servers. Stochastic Computing (SC), which uses a bit-stream to represent a number within [-1, 1] by counting the number of ones in the bit-stream, has high potential for implementing CNNs with ultra-low hardware...
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  • Write-Once Memory (WOM) code enable to transform information such that consecutive writes to the memory would have uni-directional transition of bits. This property is useful for SSD memory since it reduces the number of program-erase cycles, thus it increases the memory endurance and might and also performance impact. In this project, the students will do analysis/trade-off of new WOM codes efficiency and power/area/throughput comparison. The goal is to implement a...
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  • A vast majority of the modern digital VLSI devices utilize a technique called 'full scan' for production testing. This technique concatenates all the device registers (flip-flops or latches) in a few shift registers called 'scan chains'. In this configuration, a production tester may use the scan chains to drive logic values to the inputs of combinatorial circuits, sample the results from their outputs, output the results via the same scan...
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  • A CISC decoder is typically set up as a state machine. The machine reads the opcode field to determine what type of instruction it is, and where the other data values are. The instruction word is read in piece by piece, and decisions are made at each stage as to how the remainder of the instruction word will be read. One method to alleviate this is to use a decoded...
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  • Year - 2018
  • The RSA algorithm stood out among asymmetric encryption systems as a conceptually simple and practical encryption and authentication method which provides a near perfect level of security. Public-key cryptographic systems, such as the RSA often involve modular exponentiation (Z = Ye mod n). This widely used and computational complex operation is  performed using successive modular multiplications (C = AB mod n). The performance of such cryptosystems is primarily determined by...
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  • An advanced scalable hardware accelerator for mini batch gradient descent, targets deep-learning applications. Deep neural networks are being widely used in a large number of applications for analyzing and extracting useful information from large amount of data that is being generated every day. Inference and training are the two modes of operation of a neural network. Training is the most computationally challenging task as it involves solving a large-scale optimization...
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  • מערכות הסוחרות באופן אוטומטי בניירות ערך שינו מן היסוד את פעילות שוק ההון בשנים האחרונות. רוב המסחר בבורסות האמריקאיות מתנהל כיום ללא כל מעורבות אנושית. מכונות המסחר יכולות להיות מתוכננות לסחור במניות, אופציות, חוזים עתידיים ומוצרי מט"ח המבוססים על אוסף של כללים מוגדר מראש  הקובעים מתי לקנות, מתי למכור וכמה כסף להשקיע בכל מוצר מסחר. מערכות המסחר האוטומטיות הולכות ומשתכללות תוך עיבוד נתונים בכמות ובקצב הולכים וגדלים יחד עם קיצור...
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  • An advanced Global-Navigation-Satellite-System (GNSS) accelerator, which provides the end user with improved position, velocity and time solutions. High performance conventional GPS/GNSS receivers rely on ASIC technology to implement massive correlators, as the performance of SDR solutions is still limited. With a reasonable distribution of tasks between the host hardware and reconfigurable peripherals, a higher performance is achieved. The figure illustrates a schematic structure of a GNSS receiver, where the proposed...
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  • Memristors are resistive devices with varying resistance which depends on the voltage applied to the device. The most natural memristor application is memory. However memristors can also be used for other applications, for example logic circuits. Once such approach is MRL (Memristor Ratioed Logic) - a hybrid CMOS-memristive logic family. In MRL, OR and AND logic gates are designed using memristors. The limitation of MRL is that every memristor-based logic...
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  • Implementation of a Smallest Univalue Segment Assimilating Nucleus (SUSAN) Block
    Edge and feature extraction is one of the most important first steps in computer vision. Its main objective is to find as many useful features from a scene while keeping the output noise level to a minimum. Edge, corner and vertex detection processes serve to simplify the analysis of images by drastically reducing the amount of data to be processed.  The SUSAN principle is the basis for algorithms to perform...
  • Orthogonal Frequency Division Multiplexing (OFDM) is a Frequency Division Multiplexing (FDM) technique used as a digital multi-carrier modulation method. Instead of using one high speed channel, the data is split into a large number of lower speed channels. Orthogonal sub carriers are used to carry data on several parallel data streams which allows more efficient use of the spectrum compare to regular FDM. Orthogonality of the carriers prevents interference between...
  • The Bose, Chaudhuri, and Hocquenghem (BCH) codes form a large class of powerful random error-correcting cyclic codes. This class of codes is a remarkable generalization of the Hamming code for multiple-error correction. BCH codes are used in varied applications such as satellite communications, compact disc players, DVDs, disk drives, solid-state drives, two-dimensional bar codes, SRAMs, etc. This project proposes building a designated BCH IP core, which can be configured to...
  • Problem Definition: Network routers by nature handle thousands of mega packets per second. Each packet might come from one port and be destined to another port. The actual routing decision is made only once the packet is received and inspected. This scheme by definition, causes head of line blocking, in which one packet destined to a blocked destination completely blocks the input queue or the common processing pipeline. These kinds...
  • The RSA algorithm stood out among asymmetric encryption systems as a conceptually simple and practical encryption and authentication method which provides a near perfect level of security. Public-key cryptographic systems, such as the RSA often involve modular exponentiation (Z = Ye mod n). This widely used and computational complex operation is  performed using successive modular multiplications (C = AB mod n). The performance of such cryptosystems is primarily determined by...
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  • The RSA algorithm stood out among asymmetric encryption systems as a conceptually simple and practical encryption and authentication method which provides a near perfect level of security. Public-key cryptographic systems, such as the RSA often involve modular exponentiation (Z = Ye mod n). This widely used and computational complex operation is  performed using successive modular multiplications (C = AB mod n). The performance of such cryptosystems is primarily determined by...
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  • Although advances with silicon-based electronics continue to be made, alternative technologies are being explored. Digital circuits based on transistors fabricated from carbon nanotubes (CNTs) have the potential to outperform silicon by improving the energy–delay product, a metric of energy efficiency, by more than an order of magnitude. Hence, CNTs are an exciting complement to existing semiconductor technologies. In order to evaluate the potential of CNFETs to replace silicon CMOS technology,...
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  • The Technion's innovative TMOS sensors utilize widely available and affordable CMOS-SOI technology together with MEMS micromachining to achieve break-through in passive IR imaging. The CMOS-SOI technology allows the integration of the 2D sensors focal plane array matrix with the analog readout, which is the subject of this project. In this project, you will design, implement and simulate top level architecture for an IR camera system that includes 10x10 matrix of...
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  • A novel night vision low resolution camera is being developed in Technion. It is based on a thermally isolated floating MOS transistor used to sense temperature changes as a result of external Infrared radiation. When a constant voltage is applied to the transistor, its current signal follows the temperature variations. This current signal is read out and amplified before further processing. This is done by an integrated readout circuit (ROIC).
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  • Fast Gain-Cell Design for eDRAM-centric Design
    The need for SRAM replacement This proposal aims at replacing SRAM technology by Gain-Cell (GC) Embedded DRAM (eDRAM) in processors design. While the demand for on-die storage is increasing, the supply voltage has reached deep sub-volt level, where SRAM cells are susceptible to data corruption and information loss. Increasing the supply voltage is out of consideration since it causes dramatic increase in power consumption. We suggest replacing SRAM by GCeDRAM,...
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  • This project deals with the design and optimization of ∆∑ Algorithmic ADC conversion using the 0.18um STM technology. Delta-sigma modulation for analog-to-digital conversion resolves a number of bits which is logarithmic in the number of modulation cycles, and is linear with respect to the modulation order. As an alternative to higher-order noise shaping, an algorithmic scheme is proposed that iteratively resamples the modulation residue, by feeding the integrator output back...
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  • GMOS is a new gas sensor developed at the Technion. It is based on a thermally isolated floating MOS transistor used to sense temperature changes as a result of a chemical reaction that takes place when the gas comes in direct contact with the sensor. When a constant voltage is applied to the transistor, its current signal follows the temperature variations. This current signal should be read out and amplified...
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  • The Technion's innovative TMOS sensors utilize the widely available and affordable CMOS-SOI technology together with MEMS micromachining to a achieve break-through in passive IR imaging. The CMOS-SOI technology allows integration of the 2D sensors focal plane array matrix with the analog readout, which the subject of this project. Many types of sensors use capacitive sensing, including sensors used to detect and measure proximity, position or displacement, humidity, fluid level, and...
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  • Memristors are resistive devices with varying resistance which depends on the voltage applied to the device. The most natural memristor application is memory. However memristors can also be used for other applications, for example logic circuits. Once such approach is MRL (Memristor Ratioed Logic) - a hybrid CMOS-memristive logic family. In MRL, OR and AND logic gates are designed using memristors. The limitation of MRL is that every memristor-based logic...
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  • The growing demand to connect up the world is pushing wireless systems to be smaller than ever. This is part of the increasing move to a data driven world with billions of connected devices in the era of the Internet of Things (IoT) and space and energy are critical design criteria. Traditionally, miniaturization was possible owing to a focus in a single frequency and a single communication protocol. However, the...
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  • המעבדה מציעה פרויקטים בתחום המעגלים המשולבים בתדר רדיו הכוללים תכן של מעגלי תקשורת בתהליכי CMOS מתקדמים בתחום הננומטרי כמו 40nm ו- 28nm. הפרויקט כולל שלב של איפיון ובחינת טופולוגיות תכנוניות , ביצוע תכנון בכלי CAD מרכזיים כמו Virtuoso של Cadence ו- ADS של Keysight ,יישום תוך הכנסת שיקולי layout ובמקרים מסוימים (ורק עבור פרויקט שנתי) תהיה גם אפשרות ייצור השבב ובדיקתו. הבדיקות יתבצעו באמצעות ציוד מיוחד לבדיקת שבבים ותדר גבוה...
  • המימדים הגדולים והמחיר הגבוה של מיכשור מודרני לטיפול בסרטן ע"י הקרנה (רדיותרפיה), נגזרים בעיקר ממאיץ האלקטרונים. טכניקות ההאצה שבשימוש היום מכתיבות מאיץ באורך של מטר כדי ליצר קרינה בעלת אנרגיה גבוהה מספיק לטיפול. מחקר שמתבצע בימים אלה בפקולטה, עוסק בפיתוח מאיץ המסוגל להאיץ אלקטרונים לאנרגיות גבוהות באמצאות לייזר ומוליך גלים דיאלקטרי.
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