- Year - 2023
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In this project we will seek to answer questions such as the following: conditioned on the event that the output of the circuit is true, what is the probability that the 7th input value is false? - Year - 2022
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Resistive memories are non-volatile, dense, and CMOS compatible devices capable of addressing the scaling challenges of traditional CMOS memories. Spin torque transfer magnetoresistive RAM (STT-MRAM) is particularly advantageous for microprocessor memory structures due to the near infinite write endurance and CMOS compatible voltage levels. These devices, however, are constrained by relatively long and unpredictable write latencies that hinder integration of these devices within critical in-core applications. Just a few months... -
One of the most popular operations in personalized medicine is protein or DNA sequence database search based on pair-wise alignment, where a query sequence is compared with a database of sequences to find a highest-similarity sequence. This similarity can provide insights on the functionality of the query protein or the role of a gene. Conventional computer architecture is proven to be inefficient for personalized medicine tasks. For example, aligning even... -
New breakthroughs in physics now enable us to shape the quantum wavefunction of electrons. The goal of this project is to design new artificial atoms by using specially designed laser beams that confine electrons into novel bound states, allowing us to control their quantized energy levels. Furthermore, by shaping the electron wavefunction we can cause these atoms to have properties that are impossible with conventional atoms. For example, to create... -
The Advanced Matrix Extension (AMX), a new x86 extension designed for operating on matrices with the goal of accelerating machine learning computations. Intel’s Advanced Matrix Extensions (AMX) is a new 64-bit programming paradigm consisting of two components: A set of 2-dimensional registers (tiles) representing sub-arrays from a larger 2-dimensional memory image and an accelerator that is able to operate on tiles. In the first stage of this project, a preprocessor... -
A conventional address decoder is conceptually based on a multi-input AND gate that selects a memory row. A unique address of a memory row is set by hardwiring the direct and inverted address bits to the inputs of the AND gate. In a decoder position where the input address matches the hardwired pattern, the AND gate outputs ‘1’, selecting the memory row. The address of a memory row is permanently... -
Project description: Clustering is the task of unifying data points into groups or clusters, where the grouping of the points is commonly based as distance. Clustering has many applications including data mining, statistical data analysis, pattern recognition, and more. Two common clustering algorithms are K-Means and Density-Based Spatial Clustering of Applications with Noise (DBSCAN). With increasing needs to perform clustering on large datasets as fast as possible, running these on... -
Project Abstract: There are endless number of platforms that require implementation of video transformations, such as curve TV/computer/smartphone screens, goggles, pilot hamlet, etc. All these platforms require transformation of flat image to curved image that fits the display, so the user can see the image well without data loss. The main challenges of the core implementation are low latency (“video in => video out), high video resolutions and frame rate.... -
Background: Computing-in-memory (CiM) has been a potential solution to break the memory wall and energy wall brought by the conventional computer architecture that separates the computing units and memory units. RRAM-based stateful logic is a kind of CiM that could implement any function in RRAM crossbar array. There are some efficient synthesis and mapping methods for 2D RRAM crossbar array. 3D RRAM crossbar arrays are denser and can support stateful... -
Project description: Deep neural networks can be extraordinarily accelerated by using memristive devices as synaptic connections. However, traditionally, the deep neural networks utilize the error backpropagation algorithms, which face some issues when the networks are implemented in hardware based on memristive devices: i) complex peripheral circuits with expensive ADCs and DACs and memory back for intermediate layer states; ii) lack of efficient online training methods. We recently developed an efficient... -
Introduction: Recently, power dissipation is becoming a dominant factor in choosing the next technology. For this reason, most figures of merits currently used to test the potential of a given technology to be the next leading technology in the industry are Operations/Second x Watt or Joule/bit….and not just Operations/Second. Superconductivity is the phenomenon in which we have zero DC resistance and is viewed as a technology capable of achieving better...Categories: Analog -
Background: Processing-in-memory (PIM) solutions unite computation and memory to overcome the memory-wall, while also introducing ample opportunities for high-throughput operations. Memristive processing-in-memory is based on the memristor: an emerging fundamental device that is capable of both storage and logic by representing binary information through resistance. Efficient utilization of processing-in-memory requires rethinking many aspects of computing systems, including novel algorithmic techniques that can utilize the high-throughput of PIM. Algorithmic Paradigm:... -
Background information: Recently, several different memristive technologies (ReRAM, CBRAM, PCM and STT-MRAM) have emerged as promising candidates for digital and analog in-memory computation. Deep neural networks (DNNs) are one of the main application to benefit from analog in-memory computation. However, the noisy nature of analog computation may let to performance (“accuracy”) degradation. In this project, you will use IBM analog hardware acceleration kit, a kit developed by IBM to simulate... -
Project description: This project will focus on the implementation of an “Embedded System” which includes a System Verilog SOC design with cores, memory, accelerators, NOC (network on chip) etc. The students will work on FPGA Altera devices on which they will implement the LOTR-RISC-V fabric. Using the MMIO(Memory Mapped IO) UART/TAP interface the student will enable the FPGA to communicate with the computer via terminal and Python scripts. This project... - Year - 2021
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Reconfigurable RF integrated circuits are an attractive feature to sustain the increasing number of standards and functionalities of modern mobile devices. While back-end circuits in a radio transceiver (e.g., baseband analog, IF and digital) can be reconfigured using MOSFET switches, front-end circuits require high performance switches since resonant narrowband circuits require high quality factor inductors and capacitors. Phase-change-materials (PCM)-based RF switches have been proposed as high-performance RF switches due to... -
In computer science, a genetic algorithm (GA) is a metaheuristic inspired by the process of natural selection. Genetic algorithms are commonly used to generate high-quality solutions to optimization. They rely on on bio-inspired operators such as mutation, crossover and selection. The purpose of this project is to implement a genetic algorithm to solve the channel routing problem. -
The goal of this project is the development of an autonomous cyber protection chip for computer systems and communication channels linked to the cloud. Background: Current technology drives the accelerated development of computer components with increasing processing capabilities, bandwidth and high level of connectivity between components that maintain a constant link to the cloud. Such systems present a significant challenge in protecting the proper operation of the components. The purpose... -
STT-MRAM writes to a memory array by manipulating electron spin with a polarizing current, performs like DRAM but requires no refresh, significant reduction in switching energy compared to FS Toggle MRAM, highly scalable, enabling higher density memory products (sampling 1Gb in 2019), can interface with JEDEC DDR3 with minor modification, and is quite an attractive emerging memory. The goal of this project is to implement and simulate circuits using this device. -
An accurate, small, low-power CMOS temperature sensor for on-chip thermal monitoring will be designed and analyzed in this project. The temperature sensor utilizes the temperature characteristics of the threshold voltage of a MOS transistor to sense temperature and is quite linear over the in-temperature range (-20C, 100°C). In this project some alternative temperature sensor architectures will be analyzed during an evaluation study and the results will be compared.Categories: Analog -
In this project, a loaded-line phase shifter based on the PCM RF switch that we are developing in our group will be designed and evaluated. Phase shifters are fundamental devices to control the steer the beam in an antenna array and a great number of phase-shifters are required for this critical functionality in 5G and radar systems. PCM RF switches can increase the performance, while reducing the area overhead and... -
Project description: Orthogonal Frequency Division Multiplexing (OFDM) is a Frequency Division Multiplexing (FDM) technique used as a digital multi-carrier modulation method. Instead of using one high speed channel, the data is split into a large number of lower speed channels. Orthogonal sub carriers are used to carry data on several parallel data streams which allows more efficient use of the spectrum compare to regular FDM. Orthogonality of the carriers prevents...Categories: Verification -
The performance of integrated circuits is one of the most important design objectives in modern VLSI design. Because of very high frequencies of today’s VLSI circuits, state-of-the-art timing analysis and simulation tools should perform delay and slope calculations with very high accuracy. For this, the timing analysis tools should have two main abilities: 1) stage (cell + interconnect it drives) delay modeling and 2) methods for delay / slope propagation... -
In this project, the RF model of the indirectly heated four-terminal PCM RF switch will be improved and verified against experimental data. The model will be unified with an electro-thermal model of the device to perform optimizations of the device structure for different applications. This model will be used to explore the design constraints of these devices and to find the optimum device geometries for different applications. -
In this project some alternative SC Integrator architectures will be analyzed during an evaluation study and the results will be compared. The circuits will be designed under required performance constraints of minimal power, layout area, signal cross talks and noise reduction using advanced IC technologies.Categories: Analog -
In this project, SPnTs using the indirectly heated four-terminal PCM RF switch will be designed and simulated. The SPnTs will be designed based on the PCM fabrication process so that it can be eventually fabricated and tested. -
Recently many novel memory technologies are emerging. For example ReRAM, STT-MRAM, DRAM. All these technologies are very suitable for in memory processing. Unfortunately, at the present time, there are no actual devices and so simulating in-memory processing with these technologies is very difficult. The goal of this project is to provide a model which can be used to perform these simulations. -
This project proposes building a designated accelerator, which efficiently performs RAM-to-RAM calculations in hardware in a pipeline fashion and thereby dramatically reducing CPU load for machine-learning software applications. -
There are endless number of platforms that require implementation of video transformations, such as curved TV/computer/smartphone screens, goggles, pilot hamlet, etc. All these platforms require transformation of flat image to curved image that fits the display, so the user can see the image well without data loss. The main challenges of the core implementation are low latency (“video in => video out), high video resolutions and frame rate. The goal...
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Recent research in nanoelectronics has begun exploring the potential of carbon nanotube field effect transistors (CNFETs) as a successor to CMOS. In order to evaluate the potential of CNFETs as an alternative to silicon CMOS technology, SPICE models of CNFETs have been developed. The goal of this project is to develop a smart algorithm, based on logic effort, to design circuits more efficiently for delay optimization.Categories: Analog -
In this project, the students will develop from scratch an equivalent tool for the memristive memory processing unit (mMPU). The students will define and implement a verification methodology for verifying an mMPU instruction sequence against an equivalent CMOS logic.
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Ferroelectric Field Effect Transistor (FeFET) memory has shown the potential to meet the requirements of the growing need for fast, dense, low power and non-volatile memories.Integrating a layer of ferroelectric within the gate stack of a regular Field Effect Transistor (FET) enables the transistor to store data in the polarization state of the ferroelectric. In this project, we look for appropriate application of binary neural network (BNN) which can benefit... -
In this project, you are required to design a systolic array that efficiently implements the logic required to support per-channel activation tensor quantization for a convolution neural network. You are required to implement the design using SystemVerilog, simulate and synthesize it after which the layout will be designed. Area, power, and energy will be analyzed and compared to a conventional systolic array. Skills you will acquire: SystemVerilog, Synopsys Design Compiler,... -
In this project we will build an innovative tool that will analyze potential asymmetric aging issues in the design from an architectural and front-end point of view. The tool will inject special patterns into the design and will be assisted by special probes to identify the points of failure. -
The Bitlet model is a new an analytical, parameterized, modeling tool, developed in the ASIC2 lab. The Bitlet model can be used to estimate the performance and the power of a PIM-based system and thereby assess the affinity of workloads for PIM as opposed to traditional computing.In order to make Bitlet more beneficial, it has to be made more accessible to users by equipping it with new features and interactive graphical... -
In this project, we propose a new architecture that significantly improves reliability by reducing EM impact while relaxing the physical design efforts and significantly extending microprocessor lifetime. It is based on the observation that in many cases EM reliability issues result from excessive write activities or signals toggling in a non uniform manner. We will examine EM improvement to 3 main components of microprocessors: ALU execution unit, register file and... -
In this project, theories of the cellular nonlinear network will be studied and the possibilities of using memristive devices in these networks will be investigated. A software model of prototype cellular nonlinear neural network accounting for the behaviors of memristive devices as the synaptic connections will be implemented and a series of simulations will be performed. -
An advanced scalable hardware accelerator for deep Convolutional Auto-Encoder (CAE), targets deep-learning applications. Integrating a CAE hardware accelerator has advantages in resources occupation, operation speed, and power consumption, indicating great potential for application in digital signal processing. This project suggests building a designated acceleration IP, which efficiently performs RAM-to-RAM calculations in a pipeline fashion and thereby dramatically offloads machine-learning software applications. -
The Memristive Memory Processing Unit (mMPU) is a new process-in-memory computer architecture, which performs the computation without moving the data from the computer’s main memory (RAM). The goal of the project is to develop a sort algorithm to run on an mMPU which is based on emerging memory technology of ReRAM. -
The purpose of this project is to build a generic API that will read Verilog netlist files and will provide the users easy commands to find objects and relations in the netlist. -
Hierarchical Connectivity Models (HCM) are used to describe hardware designs using high level programming language for implementations of VLSI algorithms and automation tools. With the growing complexity of digital hardware designs (VLSI), the need for automation tools is growing rapidly. In order to implement these tools, an efficient HCM tool which parses Hardware Description Language (HDL) files into an Object-Oriented Programming (OOP) environment is required. This project purpose is... -
Sparse linear algebra is a frequent bottleneck in machine learning and data mining workloads. The efficient acceleration of sparse matrix calculations becomes even more critical when applied to big data problems. The goal is to implement an accelerator for multiplying a sparse matrix with a sparse vector. Current solutions fetch from memory all non-zero elements of the sparse matrix. The aim of this project is to implement a technique in... -
In this project some alternative low voltage thermal sensor circuits architectures will be analyzed during an evaluation study and the results will be compared. The circuits will be designed under required performance constraints of minimal power, layout area, signal cross talks and noise reduction using advanced IC technologies.Categories: Analog -
A standard solution to memory security is encrypting all data written to untrusted storage. A big problem with client-side encryption (and other systems that protect only the data itself) is that it does not protect all aspects of how the client interacts with the server's storage. Where storage is accessed, the access pattern can also reveal secret information. Suppose a patient stores his/her genome on a remote server and wishes to check... -
The DNA Sequencing process involves passing a strand of DNA through the nanopore which causes drops in the electric current passing between the walls of the pore. The amount of change in the current depends on the type of base passing through the pore. This signal is then sampled. In this project, we will design a stand-alone accelerator for the 3rd generation DNA sequence basecalling for personalized medicine applications. -
The project is to develop the SW stack for the Multi-Core RING Architecture. (C – without any external libraries). In the project the students will design a SW library for “Distributed Computing" using the embedded RING architecture.
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Clustering for unsupervised learning is an common task in machine learning systems. Several algorithms can be used for this task, for example K-Means. The main problem with K-means algorithm is the huge amount of computations. Minibatch Kmeans proposes an effective technique to drastically reduce the number of computations with an insignificant impact on the quality of the results. The goal of this project is to design and implement a hardware... -
The goal of this project is to design and implement an RTL IP (System Verilog) that will enable multiple instances of RISC-V cores to be connected in a ring configuration. The IP will consist of two main interfaces – on the one side the “Core” and the other the “Ring”. The Ring Interface will manage the data transactions on the ring - pushing and pulling RD/WR/RD_RSP transactions to/from the ring....
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RISC-V is a classic RISC architecture rebuilt for modern times. At its heart is an array of 32 registers containing the processor's running state, the data being immediately operated on, and housekeeping information. RISC-V comes in 32-bit and 64-bit variants, with register size changing to match. The goal of this project is to study the RISC-V instruction set and then to design and implement a minimal RV32I/E Core that supports...
- Year - 2020
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In this project, the students will implement a hardware design of PC to storage communication: using PCIe hardware standards and new emerging NVMe protocol. -
The goal of this project is to familiarize a future VLSI designer with a variety of cutting edge parallel programming techniques while working with an advanced massively-parallel in-memory computer. -
The project includes the simulation of the circuit both as a stand-alone and when connected to a memristor crossbar array. The simulations will include noise and parameter variations. The main tool for design and simulation is Cadence Virtuoso. -
The goal of this project is to develop algorithms for performance enhancement/cost reduction and implement it on HDL for related memory controller. The implementation includes matlab modeling, spec and architecture definition, logic design using the Verilog HDL, verification and synthesis. The emphasis of this project will be on low latency of the design. -
מערכות חישה מתקדמות בנויות ממספר הולך וגדל של טכנולוגיות חישה שונות, כגון - EO/IR/SAR. לכל טכנולוגיה ישנן יתרונות וחסרונות: - למשל מצלמת יום מאפשרת לקבל תמונה ברזולוציה מרחבית טובה מאוד בדו-מימד אך רגישה מאוד לתנאי סביבה ואינה מסוגלת לבצע הפרדה תלת מימדית - מצלמת LWIR) long wave IR) מאפשרת זיהוי אובייקטים בטמפרטורות שונות ורגישותה לתנאי סביבה טובה יותר מאשר מצלמה אופטית רגילה. - מצלמת מכ"ם (SAR) מאפשרת לקבל תמונה בכל... -
The NVM Express (NVMe) specification was introduced in 2011 and today it is the new standard storage interface for Solid-State Drives (SSD). The NVM Express specification defines a controller interface for PCIe SSD used for Enterprise and Client applications. It is based on a queue mechanism with advanced register interface, command set and feature set including error logging, status, system monitoring (SMART, health), and firmware management). The southbridge is one... -
Modern flash-based memories contain aggressive 19nm scaling of floating-gate transistors. When performing read/write/erase commands in a flash memory, the chip is occupied and cannot be used to perform other commands in parallel. It is sometimes possible to stop the instruction execution in the middle (to perform another instruction) but the penalty of return is a significant slowdown of command execution. The SSD architecture consists of multiple channels. Each has multiple... -
A vast majority of the modern digital VLSI devices utilize a technique called 'full scan' for production testing. This technique concatenates all the device registers (flip-flops or latches) in a few shift registers called 'scan chains'. In this configuration, a production tester may use the scan chains to drive logic values to the inputs of combinatorial circuits, sample the results from their outputs, output the results via the same scan... -
As the demand for high throughput increases for applications like HD 4K, VR glass, signal processing in autonomous car, a high speed chip to chip interface become a bottleneck for data transfer between components. Few examples includes RF front end communication with the application processor SOC, FPGA accelerator communications with display chip/memory, high definition 3D camera communications with DSP chip and more. In order to support the high data throughput,...Categories: Analog -
Resistive memory is a new technology based on a passive circuit element called Memristor, which changes its resistance value based on the current flowing through it. Memristors are nanoscale elements that can be easily integrated in a typical VLSI manufacturing process. Therefore, memristors can be combined with existing structures to create new circuits. Memristors have a list of unique properties, such as non-volatility, non-linearity and sensitivity to process that make...Categories: Analog -
The growing demand to connect up the world is pushing wireless systems to be smaller than ever. This is part of the increasing move to a data driven world with billions of connected devices in the era of the Internet of Things (IoT) and space and energy are critical design criteria. Traditionally, miniaturization was possible owing to a focus in a single frequency and a single communication protocol. However, the... -
המעבדה מציעה פרויקטים בתחום המעגלים המשולבים בתדר רדיו הכוללים תכן של מעגלי תקשורת בתהליכי CMOS מתקדמים בתחום הננומטרי כמו 40nm ו- 28nm. הפרויקט כולל שלב של איפיון ובחינת טופולוגיות תכנוניות , ביצוע תכנון בכלי CAD מרכזיים כמו Virtuoso של Cadence ו- ADS של Keysight ,יישום תוך הכנסת שיקולי layout ובמקרים מסוימים (ורק עבור פרויקט שנתי) תהיה גם אפשרות ייצור השבב ובדיקתו. הבדיקות יתבצעו באמצעות ציוד מיוחד לבדיקת שבבים ותדר גבוה... -
מערכות חישה מתקדמות בנויות ממספר הולך וגדל של טכנולוגיות חישה שונות, כגון - EO/IR/SAR. לכל טכנולוגיה ישנן יתרונות וחסרונות: - למשל מצלמת יום מאפשרת לקבל תמונה ברזולוציה מרחבית טובה מאוד בדו-מימד אך רגישה מאוד לתנאי סביבה ואינה מסוגלת לבצע הפרדה תלת מימדית - מצלמת LWIR) long wave IR) מאפשרת זיהוי אובייקטים בטמפרטורות שונות ורגישותה לתנאי סביבה טובה יותר מאשר מצלמה אופטית רגילה. - מצלמת מכ"ם (SAR) מאפשרת לקבל תמונה בכל... -
The negative impedance converter (NIC) is a one-port Op-Amp circuit acting as a negative load which injects energy into circuits in contrast to an ordinary load that consumes energy from them. This is achieved by adding or subtracting excessive varying voltage in series to the voltage drop across an equivalent positive impedance. This reverses the voltage polarity or the current direction of the port and introduces a phase shift of...Categories: Analog -
Reconfigurable RF integrated circuits are an attractive feature for sustaining the increasing number of standards and functionalities of modern mobile devices. While back-end circuits in a radio transceiver (e.g., baseband analog, IF and digital) can be reconfigured using MOSFET switches, front-end circuits require high performance switches since resonant narrowband circuits require high quality factor inductors and capacitors. Phase-change-materials (PCM)-based RF switches have been proposed as high-performance RF switches due to... -
The growing demand to connect the world is pushing wireless systems to be smaller than ever. This is part of the increasing move to a data driven world with billions of connected devices in the era of the Internet of Things (IoT) and space and energy are critical design criteria. Traditionally, miniaturization was possible owing to a focus in a single frequency and a single communication protocol. However, the real... -
The goal is to implement a generic system that is allowed to add input queues, output queues, with different parameters in enqueueing/dequeueing elements to/from their queues. -
A group in Intel is working on x86 test content optimization and creation using ML techniques. A working solution already exists for test content optimization in production mode. The next stage of the project is to create new content automatically by learning from legacy content (since x86 is backward compatible, huge legacy is available to learn from). Test optimization refers to the compilation of a test suit that achieves the... -
Boolean Satisfiability (SAT) is the problem of deciding if there is an assignment to the variables of a Boolean formula such that the formula evaluated to TRUE. SAT is the classical NP-complete problem, and so it is unlikely that there is a polynomial-time algorithm that solves every SAT instance. Nevertheless, there are very efficient heuristic SAT-algorithms (SAT-solvers) that are able to solve practical instances with millions of variables and clauses.... -
Stochastic Computing (SC), which uses a bit-stream to represent a number within [-1, 1] by counting the number of ones in the bit-stream, has high potential for implementing CNNs with ultra-low hardware footprint. Since multiplications and additions can be calculated using AND gates and multiplexers in SC, significant reductions in power (energy) and hardware footprint can be achieved compared to the conventional binary arithmetic implementations. In this project we will... -
The purpose of this project is to simulate the effect of changing several architecture components on the overall performance of the OOPc processor. Such parameters include: The amount of cores, the amount of simultaneous threads which can run on a core, the sizes of the internal memories and caches and the network on a chip topology.
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In order to meet strict timing constraints it is necessary to limit the number of logic levels between each register / memory / port and make sure it is not above some sort of acceptable threshold. -
A systolyic array is an homogenous array of identical processors each performing the same function and each connected to several neighbours. Such a structure is very suitable for fast and efficient implementation of machine learning algorithms. The goal of this project is to design and implement an architecture for the computation of the convolution stage of a neural network for deep learning. -
The goal is to solve an optimization problem for the electrostatic field as a function of space coordinate for a given particle trajectory and AC field. Both, pure numeric optimization methodology as well as variation of parameters methods will be used.Categories: Electromagnetic Simulations -
Modern computer architectures increasingly rely on speculation to boost instruction-level parallelism. One of the common methods is the branch prediction. There are several ways to predict whether a branch is taken or not-taken, which significantly reduce the penalty of the branch. In this project we will develop a branch prediction that is bases on neural-network. The Fast Path-Based Neural Branch Prediction can reach 5% to 7% percent misprediction depending on... -
One of the most popular operations in personalized medicine is protein or DNA sequence database search based on pair-wise alignment, where a query sequence is compared with a database of sequences to find a highest-similarity sequence. OLC-based assembly algorithms focus on finding the read-to-read overlaps, defined to be a common sequence between two reads. A read-to-read overlap is a sequence match between two reads, and occurs when local regions on... -
ReRAM is an emerging technology in both Industrial and academic communities. Compliance current (CC) is a factor that can significantly influence ReRAM potential performance. The goal of this project is to design and implement a CC measurement circuit and to perform CC measurements on ReRAM devices. -
This project proposes building a designated accelerator, which efficiently performs RAM-to-RAM calculations in hardware in a pipeline fashion and thereby dramatically reducing CPU load for machine-learning software applications.
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A deep neural network (DNN) is an artificial neural network (ANN) with multiple layers between the input and output layers. The DNN finds the correct mathematical manipulation to turn the input into the output, whether it be a linear relationship or a non-linear relationship. The goal of this project is to build a novel DNN accelerator with simultaneous multi-threading. -
A deep neural network (DNN) is an artificial neural network (ANN) with multiple layers between the input and output layers. The DNN finds the correct mathematical manipulation to turn the input into the output, whether it be a linear relationship or a non-linear relationship.Multiply-and-accumulate (MAC) operations are the core of deep neural networks (DNNs). In this project we would like to investigate to what extent the toggling of the MAC... -
Performance aspects are becoming more and more relevant in modern hardware architectures and introduce various engineering challenges in the ASIC domain.Performance plays a central role in both pre-silicon and post-silicon phases and corresponds with embedded-software architecture (e.g. real-time QoS decisions). The performance widget displays data for performance metrics of mobile devices and can be configured to monitor any performance metric. This project proposes designing and implementing a designated Performance Widget... -
In this project, the students will perform characterization of a Resistive RAM (ReRAM) Crossbar array. They will work with a packaged device that contains a few arrays. The measurement setup will be based on a set of SMUs (Source Measure Units) and a PC platform that control the measuring equipment. The students will use Python to create a set of tool that allow for automatic parameter extraction from memristive devices... -
Reverse engineering of Integrated Circuits (IC's) is a complex process that involves multiple disciplines and skills. The input to the process is usually a physical device, and the output is a human-readable specification. At the first phase, the IC passes tear down to obtain a gate-level netlist description. In the second phase, a specification is extracted. The second stage is non-trivial and involves various learning algorithms and heuristics. The purpose... -
The voltage-controlled oscillator (VCO) is a critical sub-block in communications transceivers. The role of the VCO in a transceiver and the VCO requirements will be reviewed and the necessity of GHz VCOs and the driving factors towards the monolithic integration of the VCO be examined. In addition, the VCO design techniques will be outlined and design trade-offs be explored.Categories: Analog -
In this project, the students will design and implement an algorithm for executing state machines within a memristor-based memory. Such a novel method enables implementing a processor within the memory, thus eliminating the need for an external processor in small systems, and therefore reduces the limitations of today's computer systems. -
In this project, a thermoelectrical model of the indirectly heated four-terminal PCM RF switch will be developed and verified against experimental data. This model will be useful to accurately predict the behavior of these devices and to simulate large circuits with small computational power.Categories: Analog | ElectroMagnetic/Heat/Mechanical and Device Simulations | Memristors | Memristors | RF -
The goal of this project is to implement, study and experiment with different backtracking heuristics in the winner of the latest SAT evaluation contest (SAT Race 2019). We will try to find a backtracking heuristic, which would improve the performance of the already very efficient solver. It should be noticed that we won’t need to implement any new backtracking algorithm (as the complexity of such an implementation would go beyond... -
RISC-V is a classic RISC architecture rebuilt for modern times. At its heart is an array of 32 registers containing the processor's running state, the data being immediately operated on, and housekeeping information. RISC-V comes in 32-bit and 64-bit variants, with register size changing to match. A large amount of code has been developed and written at IBM in assembly for the PowerPC processor for which no C source-code exists.... -
In this project, an RF model of the indirectly heated four-terminal PCM RF switch will be developed and verified against experimental data. This model will be useful to accurately predict the behavior of these devices and to simulate large circuits with small computational power.
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The goal of this project is to perform the complete backend design of the OFDM transmitter chip and its integrated memories. This includes : synthesis, gate level simulation, physical (layout) design and verification, timing verification, power and power grid analysis. The chip may then be submitted for fabrication. The implementation will be done in Tower CMOS 0.18u technology. -
The global community produces digital data at increasing rates, creating enormous data centers for storage.Recent research proposes replacing the traditional data storage devices with biological DNA-based device, which can store information of the scale of a data-center within a few grams of weight.In this project, the student will study the emerging technological approach, and will implement digital controller circuits for managing DNA storage device. The main goals are understanding of... -
RISC-V (pronounced "risk-five") is an open-source hardware instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles.The project began in 2010 at the University of California, Berkeley, but many contributors are volunteers not affiliated with the university. The goal of this project is to study the RISC-V instruction set and then to design and implement a basic RISC-V microprocessor that supports all the instructions. Additional features will...
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Problem Description: Network routers by nature handle thousands of mega packets per second. Each packet might come from one port and be destined to another port. The actual routing decision is made only once the packet is received and inspected. This scheme by definition, causes head of line blocking, in which one packet destined to a blocked destination completely blocks the input queue or the common processing pipeline. These kinds... -
In this project, tunable inductors using the indirectly heated four-terminal PCM RF switch will be designed and simulated. The inductor will be designed based on the PCM fabrication process so that it can be eventually fabricated and tested.
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RISC-V (pronounced "risk-five") is an open-source hardware instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles.The project began in 2010 at the University of California, Berkeley, but many contributors are volunteers not affiliated with the university. RISC-V, pronounced 'Risk-Five', is a new architecture that is available under open, free and non-restrictive licences. It has widespread industry support from chip and device makers, and is designed to... -
The goal of this project is to use multi-state registers to implement an efficient architecture of Continuous Flow Multi-Threading microprocessor. -
In this project a tunable power amplification stage will be designed and evaluated. Both stabilization techniques and matching networks will be implemented by memristor-based circuits. The project is based on advanced research. The implementation will be done in Virtuoso and/or ADS. -
Project description:Template Matching is a method for searching and finding the location of a template image in a larger image. It relies on calculating at each position of the image under examination a correlation or distortion function that measures the degree of similarity or dissimilarity to a template sub-image.Among the correlation/distortion functions proposed in literature, Normalized Cross-Correlation (NCC) and Zero mean Normalized Cross Correlation (ZNCC) are widely used due to... -
Recently many novel memory technologies are emerging. For example ReRAM, STT-MRAM, DRAM. All these technologies are very suitable for in memory processing. Unfortunately, at the present time, there are no actual devices and so simulating in-memory processing with these technologies is very difficult. The goal of this project is to provide a model which can be used to perform these simulations. -
The goal of this project is to use graph clustering algorithms for the purpose of hardware reverse engineering. The students will use the HAL (Hardware Analyzer) reverse engineering framework to convert the netlists to graph objects and apply a number of graph clustering algorithms using Python igraph library. -
Logic designs is usually comprised of two types of logic: data paths and control logic. During reverse engineering, we first try to locate the data path structures taking advantage of their regular structure. Finding these structures helps in locating major circuit elements, such as register files, adders, ALU, multipliers, etc. The distinguishing property of data paths is aggregation of bit-level operations into multibit word operations. In this project, we will... -
The goal is to design and implement the HDL of a high-performance hardware serial divider for high frequencies. Initially, at least two different division algorithms will be investigated and analyzed. The design will be parametrized so that it can be configured according to specified requirements. The divider will support a variety of input / output number representation formats.
