Multi-Channel IO Scheduler For Flash Memory

Modern flash-based memories contain aggressive 19nm scaling of floating-gate transistors. When performing read/write/erase commands in a flash memory,  the chip is occupied and cannot be used to perform other commands in parallel. It is sometimes possible to stop the instruction execution in the middle (to perform another instruction) but the penalty of return is a significant slowdown of command execution.
The SSD architecture consists of multiple channels. Each has multiple ways (packages) and each package contains several memory components. The data bus between these components can only be used serially for the stream of commands. Therefore, scheduling is of vital importance for the performance of the SSD. In this project, the student will analyze the host workload of typical applications and develop and implement an optimal scheduling policy that maximizes performance.

The students will implement a workload adaptation scheduler of read/write/erase commands scheduling to channels/ways inside the SSD. The goal is to study how workload adaptation can improve the SSD performance and to develop a scheduler that implements this technique.

Next the project will include designing the architecture and implementing it in Systemverilog. The design will then be simulated and synthesized and finally the layout will be generated using automatic layout tools.

Prerequisites: Logic Design