- Cadence_Analog_Design Manual – 6.1.8 (2022/23)
- Cadence_Analog_Design Manual – 6.1.8 (2019/20)
- Cadence_Analog_Design Manual – 6.1.8 (2018/19)
- Cadence_Analog_Design Manual – 6.1.7 (2016/17)
- Cadence_NCSIM_SystemVerilog_VHDL Manual (2023/24)
- Synopsys (2022/23) VHDL/Verilog Sim and Synthesis Tower 0.18u
- Synopsys (2020/21) VHDL/Verilog Sim and Synthesis Tower 0.18u
- Synopsys (2019/20) VHDL/Verilog Sim and Synthesis Tower 0.18u
- Using Tower 0.18u RAM Memories
- Innovus20 with Tower_0.18u
- Innovus18 with Tower_0.18u
- Innovus16 with Tower_0.18u
