- Cadence_Analog_Design Manual – 6.1.8 (2019/20)
- Cadence_Analog_Design Manual – 6.1.8 (2018/19)
- Cadence_Analog_Design Manual – 6.1.7 (2016/17)
- Cadence_Analog_Design Manual – 6.1.6 (2015/16)
- Cadence_NCSIM_SystemVerilog_VHDL Manual (2019/20)
- Cadence_NCSIM_SystemVerilog_VHDL Manual (2017/18)
- Synopsys (20020/21) VHDL/Verilog Sim and Synthesis Tower0.18u
- Synopsys (20019/20) VHDL/Verilog Sim and Synthesis Tower0.18u
- Synopsys (20017/18) VHDL/Verilog Sim and Synthesis Tower0.18u
- Synopsys (20014/15) VHDL/Verilog Sim and Synthesis Tower0.18u
- Using Tower 0.18u RAM Memories
- Innovus20 with Tower_0.18u
- Innovus18 with Tower_0.18u
- Innovus16 with Tower_0.18u