UVM Verification of VLSI Digital Designs

Short Description:

The goal of this experiment is to introduce the student to the field of functional verification of large VLSI systems. You will learn the verification methodologies used in industry and you will gain experience in using Universal Verification Methodology (UVM) the standardized methodology for functional verification.


The difficulty of performing complete function verification of a complex VLSI design is due to a number of reasons. Firstly, it is impossible to simulate every possible input scenario in a reasonable amount of time. Secondly a lot of effort is required to create a suitable set of test vectors and to evaluate the results of their simulations. Finally the user needs to know which parts of the design have not been exercised by the input scenarios simulated. In this experiment you will learn how to use the Universal Verification Methodology (UVM) to overcome the above problems. The first experiment focuses on understanding the verification methodology and how to build a standard verification environment. In the second experiment you will use the knowledge gained to perform the verification of a machine learning hardware accelerator. You will learn how to generate random and directed random inputs, use the factory mechanism, understand the importance of coverage and gain experience with transaction level modeling.

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