Encryption

  • Detection of Hardware Trojan Horses

    Hardware Trojan horses are a real concern for the last 12 years or so, especially for national security. . A few examples of what such a Trojan can do when triggered are : 1. Turn off security protections or insert a known key to the encryption engine; 2. Insert errors to cause malfunction of a critical infrastructure; 3: Leak information to an unprotected zone (for example from a privileged CPU...
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  • AES Add-on Processor for RISC-V

    RISC-V (pronounced "risk-five") is an open-source hardware instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles.The project began in 2010 at the University of California, Berkeley, but many contributors are volunteers not affiliated with the university. RISC-V, pronounced 'Risk-Five', is a new architecture that is available under open, free and non-restrictive licences. It has widespread industry support from chip and device makers, and is designed to...
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  • Hardware Reverse Engineering Analyzer Evaluation

    Reverse engineering of Integrated Circuits (IC's) is a complex process that involves multiple disciplines and skills. The input to the process is usually a physical device, and the output is a human-readable specification. At the first phase, the IC passes tear down to obtain a gate-level netlist description. In the second phase, a specification is extracted. The second stage is non-trivial and involves various learning algorithms and heuristics. The purpose...
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  • Reverse Engineering Overcoming Scan Compression Structures

    A vast majority of the modern digital VLSI devices utilize a technique called 'full scan' for production testing. This technique concatenates all the device registers (flip-flops or latches) in a few shift registers called 'scan chains'. In this configuration, a production tester may use the scan chains to drive logic values to the inputs of combinatorial circuits, sample the results from their outputs, output the results via the same scan...
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  • Design For Testability (DFT) for Logic System by Scan

    A vast majority of the modern digital VLSI devices utilize a technique called 'full scan' for production testing. This technique concatenates all the device registers (flip-flops or latches) in a few shift registers called 'scan chains'. In this configuration, a production tester may use the scan chains to drive logic values to the inputs of combinatorial circuits, sample the results from their outputs, output the results via the same scan...
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  • Design of an RSA Public-Key Encryption Processor

    The RSA algorithm stood out among asymmetric encryption systems as a conceptually simple and practical encryption and authentication method which provides a near perfect level of security. Public-key cryptographic systems, such as the RSA often involve modular exponentiation (Z = Ye mod n). This widely used and computational complex operation is  performed using successive modular multiplications (C = AB mod n). The performance of such cryptosystems is primarily determined by...
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