Energy Efficient Architectures

Primary Researcher:
From Year: 2015
To Year: 2016

Non Volatile Processor
In the era of Internet-of-Things (IoT), the computing performance demand (vision, cognitive tasks, etc.) has to be adapted with the available energy supply resources. In this context, many computing architectures have been proposed to provide significant computing power over a large range of supply voltage. Techniques involve highly-energy-efficient cores, minimization of data transfers, near-threshold and sub-threshold operation of transistors to reach the minimal energy per operation.

While efficient, these solutions still rely on conventional volatile memory technologies, and the general store energy required to store the information is not compatible anymore with the needs of deep IoT.

Emerging nonvolatile memories allow to create high-energy efficiency computing architectures operated in an extremely-wide-voltage-range, i.e., from complete turn-off to nominal voltage, as well as in near-Vt and sub-Vt conditions.

Bringing non-volatility to such systems can enable Instant-on Normally-off operation with multi-context switch can tremendously reduce the power trace of such system.

We propose in this project a holistic approach augmenting recent efforts towards high-performance ultra-low-power computing with non-volatile resistive memories. Several innovations are proposed both from a memory perspective (design of multi-context NVFF, design of multi-context multi-bank registers) and methodology (device/circuit co-optimization to optimize the energy and area of proposed blocks). To achieve this goal, a strong interaction between design, architecture, software and device will be achieved.

This research is done in collaboration with Prof. Pierre-Emmanuel Gaillardon (University of Utah) and is funded by the United States – Israel Binational Science Foundation.


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