Memories

  • Flash Memory Controller Block

    Flash memory is widely-used memory technology, used in disk-on-keys, SSDs, set-top boxes (routers, TVs etc.), cellular SIM, and more. Flash memory requires a unique memory controller, as Flash is block-addressable, has unique error handling correction properties, wear leveling management and more. Solid-state drive architectures can arrange Flash chips and controller in several topologies: channels, bus-based, full crossbar and more. In this project, the students will implement a design of controller...
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  • Error Correction/RAID Engine for DNA-Based Storage

    Project description: DNA digital data storage is defined as the process of encoding and decoding binary data to and from synthesized DNA strands. The global community produces digital data at increasing rates, creating enormous data centers for storage. Recent research proposes replacing the traditional data storage devices with biological DNA-based device, which can store information of the scale of a data-center within a few grams of weight. During DNA synthesis...
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  • DNA Memory Enhancement using Signal Processing

    Project description: DNA digital data storage is defined as the process of encoding and decoding binary data to and from synthesized DNA strands. The global community produces digital data at increasing rates, creating enormous data centers for storage. Recent research proposes replacing the traditional data storage devices with biological DNA-based device, which can store information of the scale of a data-center within a few grams of weight. During DNA synthesis...
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  • Novel Synthesis and Mapping of RRAM-based Stateful Logic on 3D RRAM

    Background: Computing-in-memory (CiM) has been a potential solution to break the memory wall and energy wall brought by the conventional computer architecture that separates the computing units and memory units. RRAM-based stateful logic is a kind of CiM that could implement any function in RRAM crossbar array. There are some efficient synthesis and mapping methods for 2D RRAM crossbar array. 3D RRAM crossbar arrays are denser and can support stateful...
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  • The Design of A Secure (Oblivious) Memory

    A standard solution to memory security is encrypting all data written to untrusted storage. A big problem with client-side encryption (and other systems that protect only the data itself) is that it does not protect all aspects of how the client interacts with the server's storage. Where storage is accessed, the access pattern can also reveal secret information. Suppose a patient stores his/her genome on a remote server and wishes to check...
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  • GUI Implementation and New Features for Bitlet

    The Bitlet model is a new an analytical, parameterized,  modeling tool, developed in the ASIC2 lab. The Bitlet model can be used to estimate the performance and the power of a PIM-based system and thereby assess the affinity of workloads for PIM as opposed to traditional computing.In order to make Bitlet more beneficial, it has to be made more accessible to users by equipping it with new features and interactive graphical...
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  • Binary Neural Network (BNN) Accelerator Implementation within Ferroelectric Memory Array

    Ferroelectric Field Effect Transistor (FeFET) memory has shown the potential to meet the requirements of the growing need for fast, dense, low power and non-volatile memories.Integrating a layer of ferroelectric within the gate stack of a regular Field Effect Transistor (FET) enables the transistor to store data in the polarization state of the ferroelectric. In this project, we look for appropriate application of binary neural network (BNN) which can benefit...
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  • Risc-V Based Emerging Memory SW Emulator – System Design

    Recently many novel memory technologies are emerging. For example ReRAM, STT-MRAM, DRAM. All these technologies are very suitable for  in memory processing. Unfortunately, at the present time, there  are no actual devices and so simulating in-memory processing with these technologies is very difficult. The goal of this project is to provide a model which can be used to perform these simulations.
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  • Risc-V Based Emerging Memory SW Emulator

    Recently many novel memory technologies are emerging. For example ReRAM, STT-MRAM, DRAM. All these technologies are very suitable for  in memory processing. Unfortunately, at the present time, there  are no actual devices and so simulating in-memory processing with these technologies is very difficult. The goal of this project is to provide a model which can be used to perform these simulations.
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  • Controller for DNA-Based Data Storage

    The global community produces digital data at increasing rates, creating enormous data centers for storage.Recent research proposes replacing the traditional data storage devices with biological DNA-based device, which can store information of the scale of a data-center within a few grams of weight.In this project, the student will study the emerging technological approach, and will implement digital controller circuits for managing DNA storage device. The main goals are understanding of...
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  • STT-MRAM Memory Controller: Optimization and New Features

    STT-MRAM writes to a memory array by manipulating electron spin with a polarizing current, performs like DRAM but requires no refresh, significant reduction in switching energy compared to FS Toggle MRAM, highly scalable, enabling higher density memory products (sampling 1Gb in 2019), can interface with JEDEC DDR3 with minor modification, and is  quite an attractive emerging memory. The goal of this project is to implement and simulate circuits using this device.
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  • Multi-Channel IO Scheduler For Flash Memory

    Modern flash-based memories contain aggressive 19nm scaling of floating-gate transistors. When performing read/write/erase commands in a flash memory,  the chip is occupied and cannot be used to perform other commands in parallel. It is sometimes possible to stop the instruction execution in the middle (to perform another instruction) but the penalty of return is a significant slowdown of command execution. The SSD architecture consists of multiple channels. Each has multiple...
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  • Implementation of an Advanced Error Correction Algorithm For Flash Memory

    Modern flash-based memories contain aggressive 19nm scaling of floating-gate transistors. As a result, data is often stored with errors due to inter-cell interference, coupling, random-telegraph noise and more. The signal-to-noise ratio becomes even worse as density increases. In order to provide reliable data storage, system controller employs error-correcting algorithms. In this project, the students will implement a design of advanced error-correction encoder and decoder. The goal is to study and...
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  • NVMe Command Encoder/Decoder

    The NVM Express (NVMe) specification was introduced in 2011 and today it is the new standard storage interface for Solid-State Drives (SSD). The NVM Express specification defines a controller interface for PCIe SSD used for Enterprise and Client applications. It is based on a queue mechanism with advanced register interface, command set and feature set including error logging, status, system monitoring (SMART, health), and firmware management). The southbridge is one...
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  • Write-Once Memory (WOM)

    Write-Once Memory (WOM) code enable to transform information such that consecutive writes to the memory would have uni-directional transition of bits. This property is useful for SSD memory since it reduces the number of program-erase cycles, thus it increases the memory endurance and might and also performance impact. In this project, the students will do analysis/trade-off of new WOM codes efficiency and power/area/throughput comparison. The goal is to implement a...
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