Novel Synthesis and Mapping of RRAM-based Stateful Logic on 3D RRAM


Computing-in-memory (CiM) has been a potential solution to break the memory wall and energy wall brought by the conventional computer architecture that separates the computing units and memory units. RRAM-based stateful logic is a kind of CiM that could implement any function in RRAM crossbar array. There are some efficient synthesis and mapping methods for 2D RRAM crossbar array. 3D RRAM crossbar arrays are denser and can support stateful logic in adjacent layers. The added dimension has created the flexibility to place the stateful logic in 3 dimensions instead of only 2 dimensions. However, there are few synthesis and mapping methods that could efficiently take advantage of the 3-dimension flexibility.

Project Goals

In this project, we will develop a new synthesis and mapping method of the RRAM-based stateful logic by exploiting the architecture of 3D RRAM crossbar array. The proposed method will be compared with the method of naively extending the conventional synthesis and mapping method for 2D crossbar to 3D in terms of cell usage, latency, and endurance.


  • Courses: Advanced Circuits and Architectures with Memristors or Introduction to VLSI
  • Skill: python

Supervisors : Minhui Zou, Eric Herbelin

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