• Verification of end-to-end functional correctness has become one of the challenging tasks in VLSI design. A wide variety of tools and methodologies have been developed to enable this task. The goal of this project is to use these tools to design and implement a UVM verification environment for an OFDM transmitter core.
    Categories:
  • Automatic Verification of the Interrupt Cause Tree
    One of the most important tools of managing ASIC systems is interrupt verification. An interrupt event is normally a single event, sometimes more but still only several at the most. The causes for the interrupt are many (in our device it can get to a few thousands and more). To indicate the cause of the interrupt, there exists a hierarchy (tree) of registers where each bit in node register points...
    Categories: