One of the most important tools of managing ASIC systems is interrupt verification. An interrupt event is normally a single event, sometimes more but still only several at the most. The causes for the interrupt are many (in our device it can get to a few thousands and more). To indicate the cause of the interrupt, there exists a hierarchy (tree) of registers where each bit in node register points to lower level node register or to a leaf register. Each bit, when asserted indicates a cause for the interrupt.
The structure of the interrupt cause tree, is part of the formal definition of every device and it is described accurately in the documentation. It is therefore essential to verify the correctness also of this part of the specification of the device.
The aim of this project is to generate an automatic set of UVM tests that check the equivalence between the implementation of the interrupt cause tree in RTL and the one specified in the documentation. The tool which is implemented in UVM, will be a set of automatic tests that explore the data structure, loaded from the definition (spec) and generate access to the relevant registers that would ensure that the RTL implementation is correct. The tests will be run on the VCS or Incisive simulator
Prerequisites: Logic Design