236503

  • Unique Algorithmic Paradigm of Processing-in-Memory

    Background: Processing-in-memory (PIM) solutions unite computation and memory to overcome the memory-wall, while also introducing ample opportunities for high-throughput operations. Memristive processing-in-memory is based on the memristor: an emerging fundamental device that is capable of both storage and logic by representing binary information through resistance. Efficient utilization of processing-in-memory requires rethinking many aspects of computing systems, including novel algorithmic techniques that can utilize the high-throughput of PIM.   Algorithmic Paradigm:...
    Categories: | |

  • Convolutional Deep Belief Nets Based on Memristive Devices

    Project description: Deep neural networks can be extraordinarily accelerated by using memristive devices as synaptic connections. However, traditionally, the deep neural networks utilize the error backpropagation algorithms, which face some issues when the networks are implemented in hardware based on memristive devices: i) complex peripheral circuits with expensive ADCs and DACs and memory back for intermediate layer states; ii) lack of efficient online training methods. We recently developed an efficient...
    Categories: | | | |

  • Novel Synthesis and Mapping of RRAM-based Stateful Logic on 3D RRAM

    Background: Computing-in-memory (CiM) has been a potential solution to break the memory wall and energy wall brought by the conventional computer architecture that separates the computing units and memory units. RRAM-based stateful logic is a kind of CiM that could implement any function in RRAM crossbar array. There are some efficient synthesis and mapping methods for 2D RRAM crossbar array. 3D RRAM crossbar arrays are denser and can support stateful...
    Categories: | | | |

  • Code Optimizer Using Advanced Matrix Extension

    The Advanced Matrix Extension (AMX), a new x86 extension designed for operating on matrices with the goal of accelerating machine learning computations. Intel’s Advanced Matrix Extensions (AMX) is a new 64-bit programming paradigm consisting of two components: A set of 2-dimensional registers (tiles) representing sub-arrays from a larger 2-dimensional memory image and an accelerator that is able to operate on tiles. In the first stage of this project, a preprocessor...
    Categories: | | |

  • Acceleration of Local Sensitivity Hashing for Genome Assembly

    High-throughput sequencing have substantially changed the way biological research is performed since the early 2000s.  These sequencing technologies obtain millions of short fragments (sequences) of DNA from a living organism to generate the organism’s DNA blueprint (genome). Thanks to these new DNA sequencing platforms, we can now investigate human genome diversity between populations, find genomic variants that are likely to cause diseases and even investigate the genomes of even ancient...
    Categories: |

  • Simulation of a Wear Leveling Algorithm

    SSD & Flash memories are memory elements which are based on electron injection to change the properties of the transistor. While this allows for a small memory element which keeps it data even when powered off – this introduces a new problem: After an unknown number of writes – the transistor can malfunction and stop working. The solution to this problem is to keep track on reads and writes across...
    Categories: |

  • Hierarchical Connectivity Model (HCM) For CAD Purposes

    Hierarchical Connectivity Models (HCM) are used to describe hardware designs using high level programming language for implementations of VLSI algorithms and automation tools. With the growing complexity of digital hardware designs (VLSI), the need for automation tools is growing rapidly. In order to implement these tools, an efficient HCM tool which parses Hardware Description Language (HDL) files into an Object-Oriented Programming (OOP) environment is required.   This project purpose is...
    Categories: |

  • Implementation of A Genetic Algorithm for Channel Routing in VLSI Circuits

    Description: The first steps in the physical design of VLSI chips are partitioning and floorplanning. Partitioning is the process of dividing the chip into smaller pieces so that each piece is easier to deal with. Floorplanning is the process of providing a shape and a location for each block. The next step is to optimally place the standard cells within each block and the file step is to perform the...
    Categories: |

  • Wire Activity Estimation for Intelligent Power-Aware Placement

    In modern VLSI technology nodes, most of energy is consumed by wires rather than by gates. However, traditional placement tools optimize for wire delay rather than for wire energy consumption. While optimizing for delay is relatively straightforward (you just need to place components of the same logic function as close to each other as possible), minimization of wire energy is more complicated. It requires an accurate estimation of wire activity...
    Categories: |

  • GUI Implementation and New Features for Bitlet

    The Bitlet model is a new an analytical, parameterized,  modeling tool, developed in the ASIC2 lab. The Bitlet model can be used to estimate the performance and the power of a PIM-based system and thereby assess the affinity of workloads for PIM as opposed to traditional computing.In order to make Bitlet more beneficial, it has to be made more accessible to users by equipping it with new features and interactive graphical...
    Categories: | | | | |

  • Identifying Datapaths in a Gate Level Netlist

    Logic designs is usually comprised of two types of logic: data paths and control logic. During reverse engineering, we first try to locate the data path structures taking advantage of their regular structure. Finding these structures helps in locating major circuit elements, such as register files, adders, ALU, multipliers, etc. The distinguishing property of data paths is aggregation of bit-level operations into multibit word operations. In this project, we will...
    Categories: | | |

  • Implementation of Partitioning for Placement of a VLSI Design

    Decomposing a system into two or more smaller parts which are relatively independent can be very useful in solving a wide variety of problems. This decomposition is called partitioning. Placement is the process in which layout blocks of a VLSI design are placed at “optimal” locations in order to minimize some cost function. The first stage of a placement algorithm involves the efficient partitioning of the design into many smaller...
    Categories: |

  • Interconnect Stage Calculator and Visualizer

    The performance of integrated circuits is one of the most important design objectives in modern VLSI design. Because of very high frequencies of today’s VLSI circuits, state-of-the-art timing analysis and simulation tools should perform delay and slope calculations with very high accuracy. For this, the timing analysis tools should have two main abilities: 1) stage (cell + interconnect it drives) delay modeling and 2) methods for delay / slope propagation...
    Categories: |

  • Power/ARM to RISC-V Assembly Converter

    RISC-V is a classic RISC architecture rebuilt for modern times. At its heart is an array of 32 registers containing the processor's running state, the data being immediately operated on, and housekeeping information.  RISC-V comes in 32-bit and 64-bit variants, with register size changing to match. A large amount of code has  been developed and written at IBM in assembly for the PowerPC processor for which no C source-code exists....
    Categories: | | | |

  • Heuristics for Backtracking in SAT

    The goal of this project is to implement, study and experiment with different backtracking heuristics in the winner of the latest SAT evaluation contest (SAT Race 2019). We will try to find a backtracking heuristic, which would improve the performance of the already very efficient solver. It should be noticed that we won’t need to implement any new backtracking algorithm (as the complexity of such an implementation would go beyond...
    Categories: |
  • Efficient Minimization of Conflicting Assumptions in MiniSAT

    Efficient Minimization of Conflicting Assumptions in MiniSAT

    Boolean Satisfiability (SAT) is the problem of deciding if there is an assignment to the variables of a Boolean formula such that the formula evaluated to TRUE. SAT is the classical NP-complete problem, and so it is unlikely that there is a polynomial-time algorithm that solves every SAT instance. Nevertheless, there are very efficient heuristic SAT-algorithms (SAT-solvers) that are able to solve practical instances with millions of variables and clauses....
    Categories: |

  • Implementation of A Genetic Algorithm for Channel Routing in VLSI Circuits

    In computer science, a genetic algorithm (GA) is a metaheuristic inspired by the process of natural selection. Genetic algorithms are commonly used to generate high-quality solutions to optimization. They rely on on bio-inspired operators such as mutation, crossover and selection. The purpose of this project is to implement a genetic algorithm to solve the channel routing problem.
    Categories: |

  • Efficient Minimization of Conflicting Assumptions in MiniSAT

    Boolean Satisfiability (SAT) is the problem of deciding if there is an assignment to the variables of a Boolean formula such that the formula evaluated to TRUE. SAT is the classical NP-complete problem, and so it is unlikely that there is a polynomial-time algorithm that solves every SAT instance. Nevertheless, there are very efficient heuristic SAT-algorithms (SAT-solvers) that are able to solve practical instances with millions of variables and clauses....
    Categories: |

  • Microprocessor Test Scenario Generation using Machine Learning Techniques

    A group in Intel is working on x86 test content optimization and creation using ML techniques. A working solution already exists for test content optimization  in production mode. The next stage of the project is to create new content automatically by learning from legacy content (since x86 is backward compatible, huge legacy is available to learn from). Test optimization refers to the compilation of a test suit that achieves the...
    Categories: | | |

  • הגדרה ומימוש של מעבד מקדים עבור מערכות חישה מרובות סנסורים

    מערכות חישה מתקדמות בנויות ממספר הולך וגדל של טכנולוגיות חישה שונות, כגון - EO/IR/SAR. לכל טכנולוגיה ישנן יתרונות וחסרונות: - למשל מצלמת יום מאפשרת לקבל תמונה ברזולוציה מרחבית טובה מאוד בדו-מימד אך רגישה מאוד לתנאי סביבה ואינה מסוגלת לבצע הפרדה תלת מימדית - מצלמת LWIR) long wave IR) מאפשרת זיהוי אובייקטים בטמפרטורות שונות ורגישותה לתנאי סביבה טובה יותר מאשר מצלמה אופטית רגילה. - מצלמת מכ"ם (SAR) מאפשרת לקבל תמונה בכל...
    Categories: |
  • Optimization of  String Key Comparison

    Optimization of  String Key Comparison

    Ordered data structures that index string keys are widespread, and provide the backbone for databases. Lookups on such data structures (e.g., balanced tree) is characterized by accessing keys that are very different from each other, at least until the traversal zooms on a small range of adjacent keys. When searching for a certain key, most comparisons are thus likely to determine the result (bigger or smaller) quickly. Many string implementations...
    Categories: |

  • Implementation of a Static Timing Analyser

    Static timing analysis is a crucial step in VLSI circuit design. It is used for validation of circuit timing requirements so that the manufactured circuit works correctly with pre-defined clock frequency. Static timing analysis is performed in different stages of VLSI design process, starting from logic description of the circuit and up to the full circuit with implemented placement and routing. In this project, students will implement a simplified timing...
    Categories: |

  • A Library for Layout Operations with TCL Interface

    Project description: Layout is the physical representation of VLSI circuit, in which all kinds of electronic devices – transistors, capacitances, resistances as well as interconnects are represented by rectangular polygons made of different materials used in semiconductor technology: different kinds of doped silicon, metals and insulators. For example, a layout of CMOS inverter is shown in the picture below. The layout shows “top view” of all polygons located at different...
    Categories: |
  • Placement Using an Artificial Neural Network

    Placement Using an Artificial Neural Network

    The first steps in the physical design of VLSI chips are partitioning and floorplanning. Partitioning is the process of dividing the chip into smaller pieces so that each piece is easier and faster to run. Floorplaning is the process of providing a shape to each piece so that the sum of the pieces is the entire chip and there are no overlaps. Artificial neural networks is a kind of a...
    Categories: |
  • Floorplan using Placement Algorithms

    Floorplan using Placement Algorithms

    The first steps in the physical design of VLSI chips are portioning and floorplanning. Partitioning is the process of dividing the chip into smaller pieces so that each piece is easier and faster to run. Floorplaning is the process of providing a shape to each piece so that the sum of the pieces is the entire chip and there are no overlaps The object of this project is to perform...
    Categories: |

  • Implementation of a Static Timing Analyser

    Static timing analysis is a crucial step in VLSI circuit design. It is used for validation of circuit timing requirements so that the manufactured circuit works correctly with pre-defined clock frequency. Static timing analysis is performed in different stages of VLSI design process, starting from logic description of the circuit and up to the full circuit with implemented placement and routing. In this project, students will implement a simplified timing...
    Categories: |

  • Stage Delay Calculator

    The performance of integrated circuits is one of the most important design objectives in modern VLSI design. Because of very high frequencies of today’s VLSI circuits, state-of-the-art timing analysis and simulation tools should perform delay and slope calculations with very high accuracy. For this, the timing analysis tools should have two main abilities: 1) stage (cell + interconnect it drives) delay modeling and 2) methods for delay / slope propagation...
    Categories: |

  • A Library for Layout Operations with TCL Interface

    Project description: Layout is the physical representation of VLSI circuit, in which all kinds of electronic devices – transistors, capacitances, resistances as well as interconnects are represented by rectangular polygons made of different materials used in semiconductor technology: different kinds of doped silicon, metals and insulators. For example, a layout of CMOS inverter is shown in the picture below. The layout shows “top view” of all polygons located at different...
    Categories: |
    Tags: |

  • Design Rules Checker Tool

    Project description: Layout is the physical representation of VLSI circuit, in which all kinds of electronic devices – transistors, capacitances, resistances as well as interconnects are represented by rectangular polygons made of different materials used in semiconductor technology: different kinds of doped silicon, metals and insulators. For example, a layout of CMOS inverter is shown in the picture below. The layout shows “top view” of all polygons located at different...
    Categories: |
    Tags: