Hierarchical Connectivity Models (HCM) are used to describe hardware designs using high level programming language for implementations of VLSI algorithms and automation tools. With the growing complexity of digital hardware designs (VLSI), the need for automation tools is growing rapidly. In order to implement these tools, an efficient HCM tool which parses Hardware Description Language (HDL) files into an Object-Oriented Programming (OOP) environment is required.
This project purpose is to implement an Application Programming Interface (API) of HCM, which will be used in the “VLSI CAD” course.
Hierarchical Connectivity Model (HCM) implementation using High Level Programming Language (C++) for Computer Aided Design (CAD) Purposes
Background:
Hierarchical Connectivity Models (HCM) are used to describe hardware designs using high level programming language for implementations of VLSI algorithms and automation tools. With the growing complexity of digital hardware designs (VLSI), the need for automation tools is growing rapidly. In order to implement these tools, an efficient HCM tool which parses Hardware Description Language (HDL) files into an Object-Oriented Programming (OOP) environment is required.
Project:
This project purpose is to implement an Application Programming Interface (API) of HCM, which will be used in the “VLSI CAD” course. The implementation will be a C++ code, to be written in Visual Studio environment. The goal is to read Verilog files and represent their components and connectivity in a dedicated data structure.
Relevant pre-knowledge:
The project mainly requires writing an OOP using C++ so previous practice with C++ and OOP is mandatory.
“046880 – VLSI CAD” course is plus (optional, but not required).
For more information:Mor Dahan – mordahan@campus.technion.ac.il