Fast Logic Level Analysis of Gate Level Schematic

In order to meet strict timing constraints it is necessary to limit the number of logic levels between each register / memory / port and make sure it is not above some sort of acceptable threshold.

The goal of this project is to implement a checker which will perfom the following tasks :

– read a gate level schematic implementation (netlist) + some input commands

– read the library file which includes a description of all the cells in the library

– analyze the netlist according to the input command

– deliver a detailed report on all violating paths posiibly with a user friendly GUI

The emphasis and main challenge is runtime. The tool is required to run in minutes, not hours for large circuits and therefore there is a need to implement an efficient database that will enable the algorithm to run very fast.

Prerequisites : Graph algorithms, background in programming