Identifying Datapaths in a Gate Level Netlist

Logic designs is usually comprised of two types of logic: data paths and control logic. During reverse engineering, we first try to locate the data path structures taking advantage of their regular structure. Finding these structures helps in locating major circuit elements, such as register files, adders, ALU, multipliers, etc. The distinguishing property of data paths is aggregation of bit-level operations into multibit word operations. In this project, we will use the WordRev tool to find data path elements in a System-on-a-Chip model.

Project description:

Background: Logic designs is usually comprised of two types of logic: data paths and control logic. During reverse engineering, we first try to locate the data path structures taking advantage of their regular structure. Finding these structures helps in locating major circuit elements, such as register files, adders, ALU, multipliers, etc. The distinguishing property of data paths is aggregation of bit-level operations into multibit word operations. The WordRev tool employs a series of algorithms to identify word-level constructs in the design. In this project, we will use the WordRev tool to find data path elements in a System-on-a-Chip model.
Project Description: In the first stage of the project, the students will integrate the WordRev tool with the HAL (Hardware Analyzer) reverse engineering framework. In the second stage, they will take a SoC benchmark from an open-source hardware design repository and synthesize it. Finally, the students will apply the WordRev technique to identify data path structures in the synthesized design.
During the project, the students will learn chip design implementation tools, will acquire experience in coding in Python (HAL interface language) and will get familiar with the hardware reverse engineering tools and practices.
Prerequisites: Logic Design, Lab 1, Basic acquaintance with Python and C++
Supervisor: Leonid Azriel (leonida@technion.ac.il)