In this project we will build an innovative tool that will analyze potential asymmetric aging issues in the design from an architectural and front-end point of view. The tool will inject special patterns into the design and will be assisted by special probes to identify the points of failure.
Background:
Chip reliability is an essential design requirement and is crucial to assure the correct functionality of a semiconductor integrated circuit (IC). For every IC, chip vendors are required to guarantee a minimum lifetime, which depends on a reliability prediction for each chip. Given the use of new advanced process technologies and new applications such as computation-intensive infrastructures (e.g., autonomous vehicles, data-center computing, cloud computing, life-support systems, etc.), the need for reliability has significantly heightened. Advanced FinFET VLSI technologies (28nm and lower) have become highly susceptible to transistor aging.
The common approach to handle such degradation in digital circuits is to provide extra timing margin to the clock cycle time to take the timing degradation into account. Unfortunately, many digital circuits may incur asymmetric transistor aging. Asymmetric may be the result of applying constant voltage to transistor gates for long period. The duration of time required for the transistor to incur such a degradation may vary between 10s of seconds up to several weeks.
Project Requirements
There are very few tools that can perform asymmetric aging analysis and many of them use a physical design-based approach.
In this project we will build an innovative tool that will analyze potential asymmetric aging issues in the design from an architectural and front-end point of view. The tool will inject special patterns into the design and will be assisted by special probes to identify the points of failure.
Asymmetric aging is highly correlated to the toggling rate of each node in the design. The goal is to design and implement a software tool that takes the verilog code (behavioural or gate level) as input and automatically inserts into the code toggle rate measurement points.
The main project stages are:
- Read the RTL of a DUT and determine the input, outputs and internal nodes.
- Automatic attachment of probes to the internal nodes.
- Automatic testbench creation – Insertion of pseudorandom binary sequence (PRBS) injectors to the DUT inputs and probing points.
- Simulation of the design – Running the DUT simulation with the generated testbench and recording the behavior of all probe points.
- Analysis – analyse the toggle rate as indicated above.
- Presentation of results – graphs, histograms etc.
The tool should create a report referring to every cell or signal in the design measuring its toggle rate. It should create histograms of the toggle rates per module/probe point and should also analyse the source or root cause of logical gates under static stress: clock gate being closed, constant inputs not being able to propagate etc.
As a case study a floating point execution unit will be used that consists of a multiplier, divider, adder and subtractor.
If time allows, the RTL will be synthesized to gate level netlist and the analysis will be repeated for the gate level representation as well.
The result of this project is targeted to be in academic paper.
Prerequisite : Digital Systems and Computer Structure – 044252
Instructor: Prof. Freddy Gabbay freddyg@technion.ac.il