The purpose of this project is to build a generic API that will read Verilog netlist files and will provide the users easy commands to find objects and relations in the netlist.
One of the things which delays some of the projects in the VLSI lab is the lack of an organized Verilog parser. Students who wish to read Verilog files need to parse them themselves.
The purpose of this project is to build a generic API that will read Verilog netlist files and will provide the users easy commands to find objects and relations in the netlist.
Prerequisites: Background in programming.
Supervisor : Amnon Stanislavsky