Design Rules Checker Tool

Project description: Layout is the physical representation of VLSI circuit, in which all kinds of electronic devices – transistors, capacitances, resistances as well as interconnects are represented by rectangular polygons made of different materials used in semiconductor technology: different kinds of doped silicon, metals and insulators. For example, a layout of CMOS inverter is shown in the picture below. The layout shows “top view” of all polygons located at different layers of die, in order to distinguish between polygons of different types, different colors are used.

In order to prevent silicon damages during fabrication, a set of Design Rules is applied to different layout elements, controlling their widths, allowed overlap and spacing dimensions. CAD tools are used to perform Design Rule Checking (DRC) in order to ensure that given layout doesn’t violate any one of rules, which will ensure defect-prune fabrication with high probability. Another check that should be done before layout is sent to fabrication is Layout versus Schematic (LVS) check. This check ensures that layout implements exactly the same functionality as corresponding schematic circuit. It mostly means that all layout elements are connected similarly to their schematic counterparts.
In this project, students will implement simple DRC tool. The layout will be passed to the tool using standard industry format. In addition, the tool will obtain a file with the design rules set. The tool will read the layout data and perform required DRC checks. Then, the tool will report found violations. The project will also include implementation of simple GUI for representation of the layout and found DRC violations.