RISC-V is a classic RISC architecture rebuilt for modern times. At its heart is an array of 32 registers containing the processor's running state, the data being immediately operated on, and housekeeping information. RISC-V comes in 32-bit and 64-bit variants, with register size changing to match.
A large amount of code has been developed and written at IBM in assembly for the PowerPC processor for which no C source-code exists. Therefore this code cannot be recompiled.This assembly code needs to be converted automatically to RISC-V assembly, as part of building a SW tool for post-silicon validation of RISC-V chips.
A large amount of code has been developed and written at IBM in assembly for the PowerPC processor for which no C source-code exists. Therefore this code cannot be recompiled.
This assembly code needs to be converted automatically to RISC-V assembly, as part of building a SW tool for post-silicon validation of RISC-V chips.
RISC-V is a classic RISC architecture rebuilt for modern times. At its heart is an array of 32 registers containing the processor’s running state, the data being immediately operated on, and housekeeping information. RISC-V comes in 32-bit and 64-bit variants, with register size changing to match.
Objectives
- Learn about the RISC-V ISA, and its tool chain
- Preferably use Python
- Prior art search
- Preferably utilize open source code
- Consider LLVM (then all you would need is to disassemble RISC-V to LLVM)
- Papers (compilation/conversion/assembly)
- The scope of this project is function-by-function conversion, not full program conversion (which is more like writing an entire compiler).
- Manual fixing of some converted functions is expected – those should be flagged as such
- Finally, the tool should be able to successfully convert a known simple c-code program (several function calls)
- Compile program both to Power/ARM ISA, and RISC-V ISA assembly
- Use tool to convert
- Conversion output should behave the same as the compiled output
Supervisor : Tom Kolan – IBM