Stage Delay Calculator

The performance of integrated circuits is one of the most important design objectives in modern VLSI design. Because of very high frequencies of today’s VLSI circuits, state-of-the-art timing analysis and simulation tools should perform delay and slope calculations with very high accuracy. For this, the timing analysis tools should have two main abilities: 1) stage (cell + interconnect it drives) delay modeling and 2) methods for delay / slope propagation through stages. The goal of this project is building high quality stage timing simulator based on modern timing modeling methods for devices and interconnect. The simulator will consist of two parts: GUI where user will be able to define types and sizes of driver and receiver cells as well as shape of driven interconnect; the core which will perform simulation itself. The GUI also will be used for displaying results