Wire Activity Estimation for Intelligent Power-Aware Placement

In modern VLSI technology nodes, most of energy is consumed by wires rather than by gates. However, traditional placement tools optimize for wire delay rather than for wire energy consumption. While optimizing for delay is relatively straightforward (you just need to place components of the same logic function as close to each other as possible), minimization of wire energy is more complicated. It requires an accurate estimation of wire activity (i.e. the frequency of signal change), which is not a simple task.

In this project, we will design a static procedure for estimating the wire activity and test it on a few selected designs. Static means that wire activity estimation will be done using Boolean algebra rather than simulation.

This is a research project, endeavoring into a new field of study, which may lead to further research and scientific publications.

 What will we do and learn in the project?

  1. Learn VLSI design tools
  2. Learn advanced Boolean algebra methods
  3. Develop a novel CAD tool for very relevant and important purpose (energy optimization)


  • Ability to work independently and endeavor into unchartered territory
  • Desire to innovate and try new things


  • 046880 (Logic CAD of VLSI)Is desired but not a must requirement – this project is the opportunity to learn the relevant subject

Supervisor : Dr. Leonid Yavits