Static timing analysis is a crucial step in VLSI circuit design. It is used for validation of circuit timing requirements so that the manufactured circuit works correctly with pre-defined clock frequency. Static timing analysis is performed in different stages of VLSI design process, starting from logic description of the circuit and up to the full circuit with implemented placement and routing.
In this project, students will implement a simplified timing analysis tool, with usage of artificial netlist, cell library and parasitic extraction file. During the project, students will be exposed to the basics of VLSI design – netlist representation, cell library characterization, timing propagation, cell delay, path delay etc. The tool will include basic functionality of static timing analysis tool as well as simple visualization capability.
Prerequisites: Programming in C++ in Linux / UNIX environment. Any course on data structures and algorithms. Familiarity with logic circuits is recommended.