The goal of this project is to use graph clustering algorithms for the purpose of hardware reverse engineering. The students will use the HAL (Hardware Analyzer) reverse engineering framework to convert the netlists to graph objects and apply a number of graph clustering algorithms using Python igraph library.
Project description:
Background: The task of Integrated Circuit (IC) reverse engineering searches for functional blocks within large scale logic circuits. When it comes to analysis of multimillion devices-size integrated circuits, the first step of analysis involves splitting the circuit into smaller subcircuits. This reduces the complexity of the following stages and allows for more efficient analysis. The circuit can be represented as a graph, which makes various graph clustering algorithms applicable to circuit partitioning. The purpose of this project is evaluation of different algorithms to find those that provide the best results, when the success criterion is correlation to the original design partitioning.
Project Description: In this project, the students will compare graph clustering algorithms using a number of circuit benchmarks. First, the students will synthesize open source logic designs from the opencores library and other sources to obtain gate-level netlists. Next, they will use the HAL (Hardware Analyzer) reverse engineering framework to convert the netlists to graph objects and apply a number of graph clustering algorithms using Python igraph library. Finally, the clustering results will be correlated to the original design hierarchy, and comparison of the algorithms will be produced.
During the project, the students will learn chip design implementation tools, will acquire experience in coding in Python (HAL interface language), will gain expertise in graph algorithms and will get familiar with the hardware reverse engineering tools and practices.
Prerequisites: Logic Design, Lab 1, Basic acquaintance with Python
Supervisor: Leonid Azriel (leonida@technion.ac.il)