Neural networks is a rapidly emerging field. The goal of this project is to perform placement of standard cells in VLSI circuits with neural networks as described in the paper "Neural Network Based Approach to cell Placement" which uses Artificial Neural Network techniques in order to do the cell placement.
Description:
The first steps in the physical design of VLSI chips are partitioning and floorplanning. Partitioning is the process of dividing the chip into smaller pieces so that each piece is easier to deal with. Floorplanning is the process of providing a shape and a location for each block. The next step is to optimally place the standard cells within each block. Although many algorithms have been proposed for VLSI cell placement, there is plenty of room for improvement as the problem is NP-complete.
Neural networks is a rapidly emerging field. The goal of this project is to perform placement of standard cells in VLSI circuits with neural networks as described in the paper “Neural Network Based Approach to cell Placement” which uses Artificial Neural Network techniques in order to do the cell placement:
https://ieeexplore.ieee.org/document/130869
The placement tool may be implemented in any language.
Prerequisites: Background in programming and data structures.