UVM Verification of an OFDM Transmitter Core

Project description:

Orthogonal Frequency Division Multiplexing (OFDM) is a Frequency Division Multiplexing (FDM) technique used as a digital multi-carrier modulation method. Instead of using one high speed channel, the data is split into a large number of lower speed channels. Orthogonal sub carriers are used to carry data on several parallel data streams which allows more efficient use of the spectrum compare to regular FDM. Orthogonality of the carriers prevents interference between the closely spaced carriers and provides high bandwidth efficiency.

The generation and modulation of multiple sinusoidal signals which is required by OFDM in hardware is a complex task. Fortunately a clever technique which involves the use of IFFT in the transmitter eliminates the need this. Recently the Systemverilog implementation has been successfully completed.

Basic simulations were performed to verify the correctness of the design, but a more comprehensive design environment is needed.

Verification of end-to-end functional correctness has become one of the challenging tasks in VLSI design. A wide variety of tools and methodologies have been developed to enable this task. The goal of this project is to use these tools to design and implement a verification environment for aOFDM transmitter core.

Project goals

●      Learning the basics of SystemVerilog verification language (commonly used in the industry)

●      Learning the basics of UVM – a proven industry-standard verification methodology based on an object-oriented programming model supported by SystemVerilog

●      Building a block-level verification environment, while experiencing in:

●      Studying the design spec, and characterizing environment modules (sequences, drivers, monitors etc.)

●      Implementing modules under UVM methodology

●      Defining test plan, regression and coverage

●      Fixing the design/verification env if necessary

Prerequisite : Digital Systems and Computer Structure – 044252