STT-MRAM writes to a memory array by manipulating electron spin with a polarizing current, performs like DRAM but requires no refresh, significant reduction in switching energy compared to FS Toggle MRAM, highly scalable, enabling higher density memory products (sampling 1Gb in 2019), can interface with JEDEC DDR3 with minor modification, and is quite an attractive emerging memory. The goal of this project is to implement and simulate circuits using this device.
Project description:
STT-MRAM writes to a memory array by manipulating electron spin with a polarizing current, performs like DRAM but requires no refresh, significant reduction in switching energy compared to FS Toggle MRAM, highly scalable, enabling higher density memory products (sampling 1Gb in 2019), can interface with JEDEC DDR3 with minor modification, and is quite an attractive emerging memory. Let’s use it!
Project Description:
Prerequisites: Computer organization and Design
Recommended: Lab1
Host: VLSI Lab
Supervisor : Eric 054- 4946383, Lab718, ericherbelin@ee.Technion.ac.il