Risc-V Based Emerging Memory SW Emulator – System Design

Recently many novel memory technologies are emerging. For example ReRAM, STT-MRAM, DRAM. All these technologies are very suitable for  in memory processing. Unfortunately, at the present time, there  are no actual devices and so simulating in-memory processing with these technologies is very difficult. The goal of this project is to provide a model which can be used to perform these simulations.

Recently many novel memory technologies are emerging. For example ReRAM, STT-MRAM, DRAM. All these technologies are very suitable for  in memory processing. Unfortunately, at the present time, there  are no actual devices and so simulating in-memory processing with these technologies is very difficult.

Project Requirements

The goal of this project is to provide a model which can be used to perform these simulations. An architecture consisting of 4 blocks: Main CPU + Memory CTRL + Memy Array Ctrlr + Memory ARRAY  will be implemented on an FPGA. The internal ARM and/or RISC-V + Memory Ctrlr library will be used for the CPU and memory controller. An RTL model will be designed and implemented for Memory Array Ctrlr + Memy ARRAY. The aim of this project is to write code  for the CPU which will enable it to configure the system for the different memory technologies.

Prerequisites : Logic Design

This project is done in co-operation with the ASIC2 (Architectures, Systems, Intelligent Computing Integrated Circuits lab).
Supervisor : Eric 054- 4946383, Lab718, ericherbelin@ee.technion.ac.il