Flash memory is widely-used memory technology, used in disk-on-keys, SSDs, set-top boxes (routers, TVs etc.), cellular SIM, and more. Flash memory requires a unique memory controller, as Flash is block-addressable, has unique error handling correction properties, wear leveling management and more.
Solid-state drive architectures can arrange Flash chips and controller in several topologies: channels, bus-based, full crossbar and more.
In this project, the students will implement a design of controller and architecture for solid-state drive. The implementation includes system matlab modeling, spec and architecture definition, logic design using the Verilog HDL, verification and synthesis.
Project goals:
· Understanding of controllers architecture and Flash memory background
· Architecture development, logic design, implementation in verilog HDL, simulation, synthesis and layout.
Prerequisite : Digital Systems and Computer Structure – 044252
Supervisor : Dr. Amit Berman