
Modern flash-based memories contain aggressive 19nm scaling of floating-gate transistors. As a result, data is often stored with errors due to inter-cell interference, coupling, random-telegraph noise and more. The signal-to-noise ratio becomes even worse as density increases. In order to provide reliable data storage, system controller employs error-correcting algorithms.
In this project, the students will implement a design of advanced error-correction encoder and decoder. The goal is to study and implement a new algorithm for BCH error-correction code with improved performance. The implementation includes matlab modeling, spec and architecture definition, logic design using the Verilog HDL, verification and synthesis. The emphasis of this project will be on low gate count of the design.
Project goals:
Understanding of modern error-correction algorithms and coding theory background.
The project requirements include learning the algorithm, designing the architecture and implementing it in Systemverilog. The design will then be simulated and synthesized and finally the layout will be generated using automatic layout tools.
Prerequisite : Digital Systems and Computer Structure – 044252