Recently many novel memory technologies are emerging. For example ReRAM, STT-MRAM, DRAM. All these technologies are very suitable for in memory processing. Unfortunately, at the present time, there are no actual devices and so simulating in-memory processing with these technologies is very difficult. The goal of this project is to provide a model which can be used to perform these simulations.
Recently many novel memory technologies are emerging. For example ReRAM, STT-MRAM, DRAM. All these technologies are very suitable for in memory processing. Unfortunately, at the present time, there are no actual devices and so simulating in-memory processing with these technologies is very difficult.
Project Requirements
The goal of this project is to provide a model which can be used to perform these simulations. An RTL implementation of a RiscV architecture will first be selected from several available options. The aim of this project is to write code for this processor which will allow it to emulate the different memory technologies. Single cell, line or array memories will be supported. An additional requirement is to implement an easy to use interface which will allow the user to configure the “software model of the memory” according to the desired memory technology.
Prerequisites : Logic Design