Design For Testability (DFT) for Logic System by Scan

A vast majority of the modern digital VLSI devices utilize a technique called 'full scan' for production testing. This technique concatenates all the device registers (flip-flops or latches) in a few shift registers called 'scan chains'. In this configuration, a production tester may use the scan chains to drive logic values to the inputs of combinatorial circuits, sample the results from their outputs, output the results via the same scan chains and check them with the expected results. This method enables testing every chip for correct behavior, and making sure no defects were inserted during chip fabrication. The full scan technique is an effective technique that allows for reaching high test coverage in a short development time. However, in applications where security is a concern, it is a serious threat. Attackers may exploit the scan chains to reverse engineer the whole device. Learning about the circuit from sampling the logic is a hard problem. However, if the attacker gets hold of the automatic test patterns (ATPG), generated by the tools, he may gain additional information from using these patterns as an oracle.

In this project, the student will develop an algorithm that learns digital circuits from scan using ATPG patterns. The students will insert scan to some digital core and run ATPG to create patterns. Further, they will build a test model that simulates scan test and test the chip with various vectors. Finally, they will use reverse engineering algorithms to learn the chip contents using ATPG vectors as an additional source of information. The project will comprise of the following:

· Picking an open source digital core for the experiment

· Synthesizing the core and inserting scan using Synopsys tools

· Running ATPG to obtain patterns

· Building a test environment and extracting values from scan

· Devloping and applying algorithms for learning the chip contents

In the course of this projects, the students will learn the chip implementation flow, i.e. synthesis , scan insertion and ATPG using Synopsys tools. In addition, they will get acquainted with the modern scan compression techniques. Finally, they will taste the art of reverse engineering

Prerequisites: Logic Design