AES Add-on Processor for RISC-V

RISC-V (pronounced "risk-five") is an open-source hardware instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles.The project began in 2010 at the University of California, Berkeley, but many contributors are volunteers not affiliated with the university.

RISC-V, pronounced 'Risk-Five', is a new architecture that is available under open, free and non-restrictive licences. It has widespread industry support from chip and device makers, and is designed to be freely extensible and customisable to fit many applications.

The goal of this project is to implement the AES algorithm on a RISC-V architecture and add an AES HW to the Standard ISA.

Project description:

RISC-V (pronounced “risk-five”) is an open-source hardware instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles.The project began in 2010 at the University of California, Berkeley, but many contributors are volunteers not affiliated with the university.

RISC-V, pronounced ‘Risk-Five’, is a new architecture that is available under open, free and non-restrictive licences. It has widespread industry support from chip and device makers, and is designed to be freely extensible and customisable to fit many applications.

RISC-V is a classic RISC architecture rebuilt for modern times. At its heart is an array of 32 registers containing the processor’s running state, the data being immediately operated on, and housekeeping information.  RISC-V comes in 32-bit and 64-bit variants, with register size changing to match. The basic architecture can be modified to suit the user’s needs.

AES (Advanced Encryption Standard) is one of the most popular encryption algorithm today. The goal of this project is to implement the AES algorithm on a RISC-V architecture and add an AES HW to the Standard ISA.

Project Description:

•Hands-on RISC-V PULPINO infrastructure
•Implement and debug AES on FPGA
•Integration in RISC-V environment
•Demonstrate advantages in terms of performance

Prerequisites : Computer organization and Design

Recommended: Lab1

Host Lab: High-Speed Digital Systems Laboratory

Eric 054- 4946383, Lab718, ericherbelin@ee.Technion.ac.il

http://asic2.group/