The goal of this project is to perform the complete backend design of the OFDM transmitter chip and its integrated memories. This includes : synthesis, gate level simulation, physical (layout) design and verification, timing verification, power and power grid analysis. The chip may then be submitted for fabrication. The implementation will be done in Tower CMOS 0.18u technology.
Orthogonal Frequency Division Multiplexing (OFDM) is a Frequency Division Multiplexing (FDM) technique used as a digital multi-carrier modulation method. Instead of using one high speed channel, the data is split into a large number of lower speed channels. Orthogonal sub carriers are used to carry data on several parallel data streams which allows more efficient use of the spectrum compare to regular FDM. Orthogonality of the carriers prevents interference between the closely spaced carriers and provides high bandwidth efficiency.
The generation and modulation of multiple sinusoidal signals which is required by OFDM in hardware is a complex task. Fortunately a clever technique which involves the use of IFFT in the transmitter eliminates the need this. Recently the Systemverilog implementation has been successfully completed.
Project Requirements:
The goal of this project is to perform the complete backend design of the OFDM transmitter chip and its integrated memories. This includes : synthesis, gate level simulation, physical (layout) design and verification, timing verification, power and power grid analysis. The chip may then be submitted for fabrication. The implementation will be done in Tower CMOS 0.18u technology.
Prerequisite : Digital Systems and Computer Structure – 044252