RISC-V is a classic RISC architecture rebuilt for modern times. At its heart is an array of 32 registers containing the processor's running state, the data being immediately operated on, and housekeeping information. RISC-V comes in 32-bit and 64-bit variants, with register size changing to match.
The goal of this project is to study the RISC-V instruction set and then to design and implement a minimal RV32I/E Core that supports all the instructions.
Full Project Description
RISC-V, pronounced ‘Risk-Five’, is a new architecture that is available under open, free and non-restrictive licences. It has widespread industry support from chip and device makers and is designed to be freely extensible and customisable to fit many applications.
RISC-V is a classic RISC architecture rebuilt for modern times. At its heart is an array of 32 registers containing the processor’s running state, the data being immediately operated on, and housekeeping information. RISC-V comes in 32-bit and 64-bit variants, with register size changing to match.
The goal of this project is to study the RISC-V instruction set and then to design and implement a minimal RV32I/E Core that supports all the instructions.
- RV32I – Base Integer Instruction Set, 32-bit.
- RV32E – Base Integer Instruction Set (embedded), 32-bit, 16 registers with a smaller instruction set.
Additional features will be added if time permits. The design will be synthesized, and the the design implemented on a FPGA.
This project will be paired with a project from the CS faculty that involves the development of the SW stack and validation package to the CPU.
As part of the students are required to write the HAS (High Level Architecture Specifications), MAS (Micro Architecture Specifications).
This project is part of an “Embedded Accelerator for Distributed Computing” system that is composed of (1) multiple RISC-V cores interconnected with a (2) Ring Controller IP and an accompanying (3) SW stack with distributed computing support. (2) and (3) implemented in separate projects.
Prerequisites: Digital Systems and Computer Structures.
Supervisors: Avi Salmon (Intel)