A conventional address decoder is conceptually based on a multi-input AND gate that selects a memory row. A unique address of a memory row is set by hardwiring the direct and inverted address bits to the inputs of the AND gate. In a decoder position where the input address matches the hardwired pattern, the AND gate outputs ‘1’, selecting the memory row. The address of a memory row is permanently linked to the physical position of the decoder row.
The project focuses on design and evaluation of a programmable address decoder, which is targeted for many applications, from fault tolerant memories through wear-leveling in resistive memories to fully associative cache and TLB.
In contrast to a conventional address decoder, a programmable resistive address decoder uses resistive elements (memristors) to program address patterns into address decoder rows. This enables the dynamic assignment of addresses to physical rows. The figure presents the concept of a programmable resistive address decoder that functions similarly to tag matching in a set associative cache. A pair of resistive elements are programmed to store an address bit. During memory access, the address is looked up in a fully- associative fashion: A pair of resistive elements also functions as an XNOR gate, comparing a bit of the input address AI to the address bit AS stored in the pair. In the case of address bit match, ‘1’ is asserted at the input of the AND gate. If all input address bits match the address bits stored in a decoder row, the AND gate outputs ‘1’, selecting the memory row.
Prerequisite : Digital Systems and Computer Structure – 044252