Modern computer architectures increasingly rely on speculation to boost instruction-level parallelism. One of the common methods is the branch prediction. There are several ways to predict whether a branch is taken or not-taken, which significantly reduce the penalty of the branch. In this project we will develop a branch prediction that is bases on neural-network. The Fast Path-Based Neural Branch Prediction can reach 5% to 7% percent misprediction depending on the “hardware budget”.
In this project the students will design a RISC CPU, which has the Fast Path-Based Neural branch prediction. The project will include a switch to turn off the branch prediction such that the performance improvement can be demonstrated.
Project description:
As the manufacturing technologies of VLSI progresses, HW architects are constantly looking for ways to improve overall performance of the CPU. In the past, many small scale architecture improvements, as well as pipelines, and other methods were used to improve performance. Other methods were increasing clock frequency and the width of data-bus, from 16 bit to 32, 64 and higher.
As the manufacturing processes become more and more dense, and the cost of gates in the core reduced on one side, and clock frequencies has almost reached a limit of usability, the road to improve performance is changing. Also other methods have reached the wall of maximum improvements, when also other factors are limiting.
All the modern CPU’s use pipelines to stagger the commands execution such that the clock frequency can be increased. Some CPU’s may have pipelines that are 32 stages deep or even more. The pipeline can work well when the flow of the program is linear, but when a branch is required, the pipeline is stalled, all it’s temporary content is discarded, as the new command is starting to step into the pipe. Since any program, includes many loops, and conditional jump commands, the performance hit of discarding the pipe is costly.
Modern computer architectures increasingly rely on speculation to boost instruction-level parallelism. One of the common methods is the branch prediction. There are several ways to predict whether a branch is taken or not-taken, which significantly reduce the penalty of the branch. In this project we will develop a branch prediction that is bases on neural-network. The earlier proposed neural branch prediction methods used history based perceptrons which had very long latency. There are new algorithms that use path-based prediction and eliminate the latency penalty, while improving the prediction success. The Fast Path-Based Neural Branch Prediction can reach 5% to 7% percent misprediction depending on the “hardware budget”.
In this project the students will design a RISC CPU, which has the Fast Path-Based Neural branch prediction. The project will include a switch to turn off the branch prediction such that the performance improvement can be demonstrated.