Implementation of a RISC-V Processor

RISC-V (pronounced "risk-five") is an open-source hardware instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles.The project began in 2010 at the University of California, Berkeley, but many contributors are volunteers not affiliated with the university. The goal of this project is to study the RISC-V instruction set and then to design and implement a basic RISC-V microprocessor that supports all the instructions. Additional features will be added if time permits. The design will be synthesized and the layout will be implemented.

RISC-V (pronounced “risk-five”) is an open-source hardware instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles.The project began in 2010 at the University of California, Berkeley, but many contributors are volunteers not affiliated with the university.

RISC-V, pronounced ‘Risk-Five’, is a new architecture that is available under open, free and non-restrictive licences. It has widespread industry support from chip and device makers, and is designed to be freely extensible and customisable to fit many applications.

RISC-V is a classic RISC architecture rebuilt for modern times. At its heart is an array of 32 registers containing the processor’s running state, the data being immediately operated on, and housekeeping information.  RISC-V comes in 32-bit and 64-bit variants, with register size changing to match.

Project Goal : The goal of this project is to study the RISC-V instruction set and then to design and implement a basic RISC-V microprocessor that supports all the instructions. Additional features will be added if time permits. The design will be synthesized and the layout will be implemented.

Prerequisites : Logic Design, Microprcessor Architectures (recommended)