Implementation of an LOTR RISC-V Based System on Chip (SOC) on an FPGA

This project will focus on the implementation of an “Embedded System” which includes a System Verilog SOC design with cores, memory,

accelerators, NOC (network on chip) etc. The students will work on FPGA Altera devices on which they will implement the LOTR-RISC-V fabric.

Using the MMIO(Memory Mapped IO) UART/TAP interface the student will enable the FPGA to communicate with the computer via terminal and Python scripts.

This project will include work:

*System Verilog –> FPGA, LOTR-RISC-V HW project – Connectivity, Integration, Interface micro design etc.

*Python –> Scripts and wrappers to enable Communication between the FPGA and the Computer CMD Terminal.

*C – > Design basic POC (Proof Of Concept) for loading programs to instruction integrated memory on the FPGA

This project will be part of the Open-Source LOTR project on github.

https://github.com/amichai-bd/riscv-multi-core-lotr

Prerequisite:  Digital Systems and Computer Structure – 044252

Supervisor : Amihai Ben David (Intel)