Network routers by nature handle thousands of mega packets per second. Each packet might come from one port and be destined to another port. The actual routing decision is made only once the packet is received and inspected.
This scheme by definition, causes head of line blocking, in which one packet destined to a blocked destination completely blocks the input queue or the common processing pipeline. These kinds of problems are commonly analyzed and solved by different techniques in the industry.
In a previous project, a detailed survey of the academic literature was performed. Several possible solutions were analyzed and modeled using high level language (C++, System C , etc.). The conclusion of this project was a proposed architecture of a router which efficiently solves the head of line blocking problem.
Design the architecture and microarchitecture of the above router. The design will then be implemented in VHDL or SystemVerilog using the C model as the reference model for simulation.
1) Implement generic system that is allowed to add input queues, output queues, with different parameters in enqueueing/dequeueing elements to/from their queues.
2) Run simulations to demonstrate the potential problems in normal ‘Round Robin’ arbitration between input queues.
3) Design an arbiter which is aware of intermediate data congestion on the output queues.
4) Perform simulations to demonstrate the overall performance improvement.
The report should include static analysis of the system, as well as dynamic analysis of the system before and after the arbitration improvement.
For more information see : http://vlsi.eelabs.technion.ac.il/projects-list/