Project description:Template Matching is a method for searching and finding the location of a template image in a larger image. It relies on calculating at each position of the image under examination a correlation or distortion function that measures the degree of similarity or dissimilarity to a template sub-image.Among the correlation/distortion functions proposed in literature, Normalized Cross-Correlation (NCC) and Zero mean Normalized Cross Correlation (ZNCC) are widely used due to their robustness in template, motion analysis stereo vision and industrial inspection.
This project suggests building a designated acceleration IP, which explores a full pipeline implementation and maximizes the internal data reuse to calculate several ZNCC-based template-matching in an efficient approach.
Project description:
Template Matching is a method for searching and finding the location of a template image in a larger image. It relies on calculating at each position of the image under examination a correlation or distortion function that measures the degree of similarity or dissimilarity to a template sub-image.
Among the correlation/distortion functions proposed in literature, Normalized Cross-Correlation (NCC) and Zero mean Normalized Cross Correlation (ZNCC) are widely used due to their robustness in template, motion analysis stereo vision and industrial inspection.
Project Requirements:
This project suggests building a designated acceleration IP, which explores a full pipeline implementation and maximizes the internal data reuse to calculate several ZNCC-based template-matching in an efficient approach. The project is highly inspired by Erika et. al paper (see references below).
The IP reads from DRAM/DMA an input frame and writes back a corresponding matching results. The IP is triggered by software Host through APB registers, and interrupts back the host when calculation is completed.
References
- Template Matching – https://en.wikipedia.org/wiki/Template_matching
- AMBA AXI – http://infocenter.arm.com/help/topic/com.arm.doc.ihi0022b/index.html
- AMBA APB – http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ihi0024c/index.html
- Albuquerque, Erika S., et al. “An FPGA-based accelerator for multiple real-time template matching.” Proceedings of the 29th Symposium on Integrated Circuits and Systems Design: Chip on the Mountains. IEEE Press, 2016.
Previous knowledge required
Logic Design
Design goals and challenges
- Learning the basics of Verilog RTL coding language (commonly used in the industry).
- Learning the basics of communication protocols, hereby AMBA APB/AXI.
- Learning Image-Processing standards which are commonly used in the industry.
- Practice in coding design using arch. spec., ramping up an advanced accelerator as an IP.