In this project, we propose a new architecture that significantly improves reliability by reducing EM impact while relaxing the physical design efforts and significantly extending microprocessor lifetime. It is based on the observation that in many cases EM reliability issues result from excessive write activities or signals toggling in a non uniform manner. We will examine EM improvement to 3 main components of microprocessors: ALU execution unit, register file and cache memory. For every such component we will examine its EM susceptibility before and after applying the architectural enhancements.
Background:
Chip reliability is an essential design requirement and is crucial to assure the correct functionality of a semiconductor integrated circuit (IC). Given the use of new advanced process technologies and new applications such as computation-intensive infrastructures (e.g., autonomous vehicles, data-center computing, cloud computing, life-support systems, etc.), the need for reliability has significantly heightened. Advanced VLSI technologies (28nm and lower) have become highly susceptible to Electro Migration due to the shrinking dimensions, the increasing density of logical elements, and the challenging voltage and temperature operating conditions.
EM is a phenomenon related to the reliability of wires and vias in ICs and is caused by excessive current flow that can potentially damage a physical device. Such damage may either reduce a wire’s conductivity or causethe wire disconnect, both of which lead to reliability concerns. To date, the design community has focused on enhancing chip-design implementation flow to solve EM issues, whereas few works have proposed architectural solutions.
Project Requirements
In this project, we propose a new architecture that significantly improves reliability by reducing EM impact while relaxing the physical design efforts and significantly extending microprocessor lifetime. It is based on the observation that in many cases EM reliability issues result from excessive write activities or signals toggling in a non uniform manner. We will examine EM improvement to 3 main components of microprocessors: ALU execution unit, register file and cache memory. For every such component we will examine its EM susceptibility before and after applying the architectural enhancements.
The main project stages are:
1. Write in Verilog basic building blocks of ALU, register files and SRAM based L1 cache.
2. Write the blocks in Verilog with EM-aware architectural enhancements e.g. periodic rotation and change the mapping of architectural register to physical register.
3. Synthesize the design and perform place-and-route
4. Extract signal toggling vector from functional simulation
5. Use the signal EM analysis using Voltus simulation environment on the design after place and route.
6. Analyze and report the EM enhancement using Voltus before and after applying the architectural enhancements.
Prerequisite: Digital Systems and Computer Structure – 044252
Instructor: Prof. Freddy Gabbay freddyg@technion.ac.il
For more information, please contact Goel Samuel Room