NMT – Near Memory Threading Using MTJ Based Multi-state Register

The goal of this project is to use multi-state registers to implement an efficient architecture of Continuous Flow Multi-Threading microprocessor.

Project description:

Just a few months ago 22nm GlobalFoundries libraries of MTJ based on EVERSPIN TECHNOLOGY were made available . A basic block of Continuous Flow Multi-Threading was designed and implemented. The goal now is to explore extending threading near the memories especially near non volatile memories, and also for near and in-memory processing.

Project Description:

• Read Papers, hands-on VLSI tools & library integration
• Learn about multi-state register implementation, memory controllers and memory arrays internals
• Explore pointer chasing and basic search operations
• Define a controller architecture and design a MPR Verilog model
• Integrate and simulate

Prerequisites: Computer organization and Design

Recommended: Lab1

Host: VLSI Lab

Supervisors : Kunal, Eric: 054- 4946383, Lab718, ericherbelin@ee.Technion.ac.il