The goal of this project is to design and implement an RTL IP (System Verilog) that will enable multiple instances of RISC-V cores to be connected in a ring configuration. The IP will consist of two main interfaces – on the one side the “Core” and the other the “Ring”. The Ring Interface will manage the data transactions on the ring - pushing and pulling RD/WR/RD_RSP transactions to/from the ring. The core interface will manage the communication with the RISC-V core.

Full Project Description
RISC-V is a classic RISC architecture rebuilt for modern times. At its heart is an array of 32 registers containing the processor’s running state, the data being immediately operated on, and housekeeping information. RISC-V comes in 32-bit and 64-bit variants, with register size changing to match.
The goal of this project is to design and implement an RTL IP (System Verilog) that will enable multiple instances of RISC-V cores to be connected in a ring configuration. The IP will consist of two main interfaces – on the one side the “Core” and the other the “Ring”. The Ring Interface will manage the data transactions on the ring – pushing and pulling RD/WR/RD_RSP transactions to/from the ring. It will also allow multiple simultaneous RD/WR data transactions from different cores to any one of the MMIO memory regions. (MMIO – Memory Mapped IO). The core interface will manage the communication with the RISC-V core.
As part of the students are required to write the HAS (High Level Architecture Specifications), MAS (Micro Architecture Specifications).
This project is part of an “Embedded Accelerator for Distributed Computing” system that is composed of (1) multiple RISC-V cores interconnected with a (2) Ring Controller IP and an accompanying (3) SW stack with distributed computing support. (1) and (3) implemented in separate projects.
Prerequisites: Digital Systems and Computer Structures.
Supervisors: Avi Salmon (Intel)