The goal of this project is to develop algorithms for performance enhancement/cost reduction and implement it on HDL for related memory controller. The implementation includes matlab modeling, spec and architecture definition, logic design using the Verilog HDL, verification and synthesis. The emphasis of this project will be on low latency of the design.
New memory devices, such as PCM and ReRAM have the potential of replacing DRAM/Flash in the future. While these devices enable further scaling and vertical stacking, their cost (bit/cell size) is higher than flash and their performance is lower than DRAM. In this project, the students will develop algorithms for performance enhancement/cost reduction and implement it on HDL for related memory controller. The implementation includes matlab modeling, spec and architecture definition, logic design using the Verilog HDL, verification and synthesis. The emphasis of this project will be on low latency of the design.
Project goals:
· Understanding the characteristics the new memory devices and developing algorithms to optimize their performance.
· Architecture development, logic design, implementation in Verilog HDL, simulation, synthesis and layout.
For more information, please contact Goel Samuel Room 711 Mayer Building, tel 4668, goel@ee.technion.ac.il
To view the VLSI projects classified according to different VLSI areas, see VLSI lab site :
http://webee.technion.ac.il/vlsi/Info/Projects/Projects_Projects_List_Main.html