Projects Archive

  • Year - 2018
  • The Bose, Chaudhuri, and Hocquenghem (BCH) codes form a large class of powerful random error-correcting cyclic codes. This class of codes is a remarkable generalization of the Hamming code for multiple-error correction. BCH codes are used in varied applications such as satellite communications, compact disc players, DVDs, disk drives, solid-state drives, two-dimensional bar codes, SRAMs, etc. This project proposes building a designated BCH IP core, which can be configured to...
  • Problem Definition: Network routers by nature handle thousands of mega packets per second. Each packet might come from one port and be destined to another port. The actual routing decision is made only once the packet is received and inspected. This scheme by definition, causes head of line blocking, in which one packet destined to a blocked destination completely blocks the input queue or the common processing pipeline. These kinds...
  • The RSA algorithm stood out among asymmetric encryption systems as a conceptually simple and practical encryption and authentication method which provides a near perfect level of security. Public-key cryptographic systems, such as the RSA often involve modular exponentiation (Z = Ye mod n). This widely used and computational complex operation is  performed using successive modular multiplications (C = AB mod n). The performance of such cryptosystems is primarily determined by...
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  • The RSA algorithm stood out among asymmetric encryption systems as a conceptually simple and practical encryption and authentication method which provides a near perfect level of security. Public-key cryptographic systems, such as the RSA often involve modular exponentiation (Z = Ye mod n). This widely used and computational complex operation is  performed using successive modular multiplications (C = AB mod n). The performance of such cryptosystems is primarily determined by...
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  • Although advances with silicon-based electronics continue to be made, alternative technologies are being explored. Digital circuits based on transistors fabricated from carbon nanotubes (CNTs) have the potential to outperform silicon by improving the energy–delay product, a metric of energy efficiency, by more than an order of magnitude. Hence, CNTs are an exciting complement to existing semiconductor technologies. In order to evaluate the potential of CNFETs to replace silicon CMOS technology,...
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  • The Technion's innovative TMOS sensors utilize widely available and affordable CMOS-SOI technology together with MEMS micromachining to achieve break-through in passive IR imaging. The CMOS-SOI technology allows the integration of the 2D sensors focal plane array matrix with the analog readout, which is the subject of this project. In this project, you will design, implement and simulate top level architecture for an IR camera system that includes 10x10 matrix of...
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  • A novel night vision low resolution camera is being developed in Technion. It is based on a thermally isolated floating MOS transistor used to sense temperature changes as a result of external Infrared radiation. When a constant voltage is applied to the transistor, its current signal follows the temperature variations. This current signal is read out and amplified before further processing. This is done by an integrated readout circuit (ROIC).
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  • Fast Gain-Cell Design for eDRAM-centric Design
    The need for SRAM replacement This proposal aims at replacing SRAM technology by Gain-Cell (GC) Embedded DRAM (eDRAM) in processors design. While the demand for on-die storage is increasing, the supply voltage has reached deep sub-volt level, where SRAM cells are susceptible to data corruption and information loss. Increasing the supply voltage is out of consideration since it causes dramatic increase in power consumption. We suggest replacing SRAM by GCeDRAM,...
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  • This project deals with the design and optimization of ∆∑ Algorithmic ADC conversion using the 0.18um STM technology. Delta-sigma modulation for analog-to-digital conversion resolves a number of bits which is logarithmic in the number of modulation cycles, and is linear with respect to the modulation order. As an alternative to higher-order noise shaping, an algorithmic scheme is proposed that iteratively resamples the modulation residue, by feeding the integrator output back...
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  • GMOS is a new gas sensor developed at the Technion. It is based on a thermally isolated floating MOS transistor used to sense temperature changes as a result of a chemical reaction that takes place when the gas comes in direct contact with the sensor. When a constant voltage is applied to the transistor, its current signal follows the temperature variations. This current signal should be read out and amplified...
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  • The Technion's innovative TMOS sensors utilize the widely available and affordable CMOS-SOI technology together with MEMS micromachining to a achieve break-through in passive IR imaging. The CMOS-SOI technology allows integration of the 2D sensors focal plane array matrix with the analog readout, which the subject of this project. Many types of sensors use capacitive sensing, including sensors used to detect and measure proximity, position or displacement, humidity, fluid level, and...
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  • Memristors are resistive devices with varying resistance which depends on the voltage applied to the device. The most natural memristor application is memory. However memristors can also be used for other applications, for example logic circuits. Once such approach is MRL (Memristor Ratioed Logic) - a hybrid CMOS-memristive logic family. In MRL, OR and AND logic gates are designed using memristors. The limitation of MRL is that every memristor-based logic...
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  • The growing demand to connect up the world is pushing wireless systems to be smaller than ever. This is part of the increasing move to a data driven world with billions of connected devices in the era of the Internet of Things (IoT) and space and energy are critical design criteria. Traditionally, miniaturization was possible owing to a focus in a single frequency and a single communication protocol. However, the...
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  • המעבדה מציעה פרויקטים בתחום המעגלים המשולבים בתדר רדיו הכוללים תכן של מעגלי תקשורת בתהליכי CMOS מתקדמים בתחום הננומטרי כמו 40nm ו- 28nm. הפרויקט כולל שלב של איפיון ובחינת טופולוגיות תכנוניות , ביצוע תכנון בכלי CAD מרכזיים כמו Virtuoso של Cadence ו- ADS של Keysight ,יישום תוך הכנסת שיקולי layout ובמקרים מסוימים (ורק עבור פרויקט שנתי) תהיה גם אפשרות ייצור השבב ובדיקתו. הבדיקות יתבצעו באמצעות ציוד מיוחד לבדיקת שבבים ותדר גבוה...
  • המימדים הגדולים והמחיר הגבוה של מיכשור מודרני לטיפול בסרטן ע"י הקרנה (רדיותרפיה), נגזרים בעיקר ממאיץ האלקטרונים. טכניקות ההאצה שבשימוש היום מכתיבות מאיץ באורך של מטר כדי ליצר קרינה בעלת אנרגיה גבוהה מספיק לטיפול. מחקר שמתבצע בימים אלה בפקולטה, עוסק בפיתוח מאיץ המסוגל להאיץ אלקטרונים לאנרגיות גבוהות באמצאות לייזר ומוליך גלים דיאלקטרי.
  • Recent research in nanoelectronics has begun to explore the potential of carbon nanotube field effect transistors (CNFETs) as a successor to CMOS. Studies of individual carbon nanotubes have demonstrated that they have excellent electrical properties, including high electron mobility. Experiments with CNFETs have further demonstrated that these devices have large transconductances, which indicates a great potential for nanoelectronic circuits. One of the challenges the CNT-FET industry is facing these days...
  • Automatic Verification of the Interrupt Cause Tree
    One of the most important tools of managing ASIC systems is interrupt verification. An interrupt event is normally a single event, sometimes more but still only several at the most. The causes for the interrupt are many (in our device it can get to a few thousands and more). To indicate the cause of the interrupt, there exists a hierarchy (tree) of registers where each bit in node register points...
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  • A novel night vision low resolution camera is being developed in Technion. It is based on a thermally isolated floating MOS transistor used to sense temperature changes as a result of external Infrared radiation. When a constant voltage is applied to the transistor, its current signal follows the temperature variations. This current signal is read out and amplified before further processing. This is done by an integrated readout circuit (ROIC).
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  • Thermal-Aware VLSI Floorplanning
    The first steps in the physical design of VLSI chips are partitioning and floorplanning. Partitioning is the process of dividing the chip into smaller pieces so that each piece is easier and faster to run. Floorplaning is the process of providing a shape to each piece so that the sum of the pieces is the entire chip and there are no overlaps The object of this project is to perform...
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  • Clock is the crucial component of any modern VLSI circuit. Clock distribution network is usually has a form of a mutli-stage buffer tree with main clock driver at the root and clock consumers (sequential elements – flip-flops and latches) at leafs. The process of creation of the clock tree is called Clock Tree Synthesis (CTS) and it is very important stage in VLSI design process. The CTS problem can be...
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  • The performance of integrated circuits is one of the most important design objectives in modern VLSI design. Because of very high frequencies of today’s VLSI circuits, state-of-the-art timing analysis and simulation tools should perform delay and slope calculations with very high accuracy. For this, the timing analysis tools should have two main abilities: 1) stage (cell + interconnect it drives) delay modeling and 2) methods for delay / slope propagation...
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  • Static timing analysis is a crucial step in VLSI circuit design. It is used for validation of circuit timing requirements so that the manufactured circuit works correctly with pre-defined clock frequency. Static timing analysis is performed in different stages of VLSI design process, starting from logic description of the circuit and up to the full circuit with implemented placement and routing. In this project, students will implement a simplified timing...
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  • Efficient Minimization of Conflicting Assumptions in MiniSAT
    Boolean Satisfiability (SAT) is the problem of deciding if there is an assignment to the variables of a Boolean formula such that the formula evaluated to TRUE. SAT is the classical NP-complete problem, and so it is unlikely that there is a polynomial-time algorithm that solves every SAT instance. Nevertheless, there are very efficient heuristic SAT-algorithms (SAT-solvers) that are able to solve practical instances with millions of variables and clauses....
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  • Floorplan using Placement Algorithms
    The first steps in the physical design of VLSI chips are portioning and floorplanning. Partitioning is the process of dividing the chip into smaller pieces so that each piece is easier and faster to run. Floorplaning is the process of providing a shape to each piece so that the sum of the pieces is the entire chip and there are no overlaps The object of this project is to perform...
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  • Placement Using an Artificial Neural Network
    The first steps in the physical design of VLSI chips are partitioning and floorplanning. Partitioning is the process of dividing the chip into smaller pieces so that each piece is easier and faster to run. Floorplaning is the process of providing a shape to each piece so that the sum of the pieces is the entire chip and there are no overlaps. Artificial neural networks is a kind of a...
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  • Project description: Layout is the physical representation of VLSI circuit, in which all kinds of electronic devices – transistors, capacitances, resistances as well as interconnects are represented by rectangular polygons made of different materials used in semiconductor technology: different kinds of doped silicon, metals and insulators. For example, a layout of CMOS inverter is shown in the picture below. The layout shows “top view” of all polygons located at different...
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  • Static timing analysis is a crucial step in VLSI circuit design. It is used for validation of circuit timing requirements so that the manufactured circuit works correctly with pre-defined clock frequency. Static timing analysis is performed in different stages of VLSI design process, starting from logic description of the circuit and up to the full circuit with implemented placement and routing. In this project, students will implement a simplified timing...
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  • Optimization of  String Key Comparison
    Ordered data structures that index string keys are widespread, and provide the backbone for databases. Lookups on such data structures (e.g., balanced tree) is characterized by accessing keys that are very different from each other, at least until the traversal zooms on a small range of adjacent keys. When searching for a certain key, most comparisons are thus likely to determine the result (bigger or smaller) quickly. Many string implementations...
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  • Year - 2017
  • Description: The project is an OpenSPARC T1-based SoC which includes: – Full or reduced OpenSPARC T1 CPU core – OpenSPARC FPU – Bridge to connect the CPU and FPU to the Whisbone bus – Nor flash controller – UART – OpenCores ethernet controller – Bridges from Whishbone to Altera and Xilinx DRAM controllers The goal of this project is to perform the complete backend design of a OpenSPARC T1 microprocessor...
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  • In this project, you will implement optical G-MOS detectors based on CMOS-SOI-MEMS technology. You will be responsible for the device coupled electrical/thermal and mechanical behavior requirements, analysis and specifications definition.
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  • The goal of this project is to design an algorithm to detect and correct such errors. The scheme relies on a coding technique that incorporates the side information of fast detrapping during the encoding stage. The implementation includes matlab modeling, spec and architecture definition, logic design using the Verilog HDL, verification and synthesis.
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  • Year - 2016
  • Project description: Layout is the physical representation of VLSI circuit, in which all kinds of electronic devices – transistors, capacitances, resistances as well as interconnects are represented by rectangular polygons made of different materials used in semiconductor technology: different kinds of doped silicon, metals and insulators. For example, a layout of CMOS inverter is shown in the picture below. The layout shows “top view” of all polygons located at different...
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  • Project description: Layout is the physical representation of VLSI circuit, in which all kinds of electronic devices – transistors, capacitances, resistances as well as interconnects are represented by rectangular polygons made of different materials used in semiconductor technology: different kinds of doped silicon, metals and insulators. For example, a layout of CMOS inverter is shown in the picture below. The layout shows “top view” of all polygons located at different...
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