Design of an Arithmetic Logic Unit using Complementary Memristor Ratioed Logic

Memristors are resistive devices with varying resistance which depends on the voltage applied to the device. The most natural memristor application is memory. However memristors can also be used for other applications, for example logic circuits. Once such approach is MRL (Memristor Ratioed Logic) - a hybrid CMOS-memristive logic family. In MRL, OR and AND logic gates are designed using memristors.

The limitation of MRL is that every memristor-based logic element (OR or AND) is followed by a CMOS inverter. Another limitation of MRL is that NOT functionality cannot be implemented by memristors.
We are proposing a new approach, called Complementary Memristor Ratioed Logic (CMRL), which is intended to fix these two issues. CMRL exploits the De Morgan law and complements each AND with an OR (and vice versa) with complementary inputs:

While CMRL requires twice as many memristors compared to MRL, it allows designing entire logic circuits using memristors only, without the need to complete each AND or OR by a CMOS inverter:

In this project, we will design a CMRL based ALU.

This is a research project, endeavoring into a very new field of study, which may lead to further research and scientific publications.
What will we do and learn in the project?
1. Learn VLSI design tools
2. Learn VLSI design flow
3. Design a novel CMRL based ALU that may revolutionize the way we design logic
4. Any ideas you will have along the way…
• Ability to work independently and endeavor into unchartered territory
• Desire to innovate and try new things
• No prior VLSI design or memristor knowledge is required – this project is the opportunity to learn the subjects.

Prerequisites: Logic Design