The project is an OpenSPARC T1-based SoC which includes:
– Full or reduced OpenSPARC T1 CPU core
– OpenSPARC FPU
– Bridge to connect the CPU and FPU to the Whisbone bus
– Nor flash controller
– OpenCores ethernet controller
– Bridges from Whishbone to Altera and Xilinx DRAM controllers
The goal of this project is to perform the complete backend design of a OpenSPARC T1 microprocessor chip. This includes : synthesis, gate level simulation, physical (layout) design and verification, timing verification, power and power grid analysis. The implementation will be done in Tower CMOS 0.18u technology.
The students will gain in depth experience of the tasks involved in a comprehensive backend design flow and will use the latest sophisticated tools from the leading CAD software vendors.
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